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| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-05 09:54:21 +0000 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-13 14:05:47 +0000 |
| commit | 5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23 (patch) | |
| tree | d5918159a05a43b97db0777f4267c4248082a000 /docs | |
| parent | 75a1ada95efa78e4133bdd947c64944005a8e5c2 (diff) | |
| download | platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.tar.gz platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.tar.bz2 platform_external_arm-trusted-firmware-5f2c690d0ea92e31cbe9d450f36fc7cbb39a9b23.zip | |
Cortex-A15: Implement workaround for errata 827671
This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html
Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/cpu-specific-build-macros.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index a9ed9c1b4..8c951de00 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -76,6 +76,9 @@ For Cortex-A15, the following errata build flags are defined : - ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. +- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 + CPU. This needs to be enabled only for revision >= r3p0 of the CPU. + For Cortex-A53, the following errata build flags are defined : - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all |