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author | johpow01 <john.powell@arm.com> | 2020-12-15 19:02:18 -0600 |
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committer | John <john.powell@arm.com> | 2020-12-18 17:41:23 +0000 |
commit | 3f0d83695cdad443a11fff9679019735021c445d (patch) | |
tree | 198ee4c9ef24d1603905d4c9ed0fefada34f34bb /docs | |
parent | 2773536b171ffdc460891d33b3347f9df313a5fc (diff) | |
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Workaround for Cortex A76 erratum 1946160
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions
of the A76 processor core. The workaround is to insert a DMB ST before
acquire atomic instructions without release semantics. This issue is
present in revisions r0p0 - r4p1 but this workaround only applies to
revisions r3p0 - r4p1, there is no workaround for older versions.
SDEN can be found here:
https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
Diffstat (limited to 'docs')
-rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index e901e0c5e..d859cc581 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -249,6 +249,9 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. +- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 + CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. + For Cortex-A77, the following errata build flags are defined : - ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 |