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| author | davidcunado-arm <david.cunado@arm.com> | 2017-10-21 22:18:48 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-10-21 22:18:48 +0100 |
| commit | 623c43774a2d1c923a6d886da34dbb78fcac62a4 (patch) | |
| tree | 60ea7939efc1989825c7d67f251d91c45f159c81 /docs/user-guide.rst | |
| parent | 6de7c00c14aefeda0de6c5f8d22787bc217053d9 (diff) | |
| parent | c639e8ebeeb152fc32f2feff65c84a37825400b3 (diff) | |
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Merge pull request #1130 from jeenu-arm/gic-patches
New GIC APIs and specifying interrupt propertes
Diffstat (limited to 'docs/user-guide.rst')
| -rw-r--r-- | docs/user-guide.rst | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/docs/user-guide.rst b/docs/user-guide.rst index 7c0a980f5..28483f2b1 100644 --- a/docs/user-guide.rst +++ b/docs/user-guide.rst @@ -386,6 +386,19 @@ Common build options images will include support for Trusted Board Boot, but the FIP and FWU\_FIP will not include the corresponding certificates, causing a boot failure. +- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have + inherent support for specific EL3 type interrupts. Setting this build option + to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both + by `platform abstraction layer`__ and `Interrupt Management Framework`__. + This allows GICv2 platforms to enable features requiring EL3 interrupt type. + This also means that all GICv2 Group 0 interrupts are delivered to EL3, and + the Secure Payload interrupts needs to be synchronously handed over to Secure + EL1 for handling. The default value of this option is ``0``, which means the + Group 0 interrupts are assumed to be handled by Secure EL1. + + .. __: `platform-interrupt-controller-API.rst` + .. __: `interrupt-framework-design.rst` + - ``HANDLE_EA_EL3_FIRST``: When defined External Aborts and SError Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. |