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| author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-05 16:25:25 +0100 |
|---|---|---|
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-17 13:46:43 +0100 |
| commit | cba71b70ef7070bcd38a8d202f30e58f79e36c6b (patch) | |
| tree | 599730f99e105a55b1733af839730a6cc204bc23 /docs/image-terminology.rst | |
| parent | 5d149bdb18c0c6fb0aa76f32e0ffbb9f9269c994 (diff) | |
| download | platform_external_arm-trusted-firmware-cba71b70ef7070bcd38a8d202f30e58f79e36c6b.tar.gz platform_external_arm-trusted-firmware-cba71b70ef7070bcd38a8d202f30e58f79e36c6b.tar.bz2 platform_external_arm-trusted-firmware-cba71b70ef7070bcd38a8d202f30e58f79e36c6b.zip | |
Cortex-A35: Implement workaround for errata 855472
Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.
Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'docs/image-terminology.rst')
0 files changed, 0 insertions, 0 deletions