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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-01-17 13:46:48 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-01-24 22:34:50 +0900 |
| commit | 7af2131787ed1e5a4fea17f17d13967d13f7d9ee (patch) | |
| tree | 346ad81dd39f05c0eb65dfdd7b6457baa9e1e61a /docs/design/cpu-specific-build-macros.rst | |
| parent | c64873ab94cbb7cc7860ed348f0c55a9dec146e4 (diff) | |
| download | platform_external_arm-trusted-firmware-7af2131787ed1e5a4fea17f17d13967d13f7d9ee.tar.gz platform_external_arm-trusted-firmware-7af2131787ed1e5a4fea17f17d13967d13f7d9ee.tar.bz2 platform_external_arm-trusted-firmware-7af2131787ed1e5a4fea17f17d13967d13f7d9ee.zip | |
uniphier: make all BL images completely position-independent
This platform supports multiple SoCs. The next SoC will still keep
quite similar architecture, but the memory base will be changed.
The ENABLE_PIE improves the maintainability and usability. You can reuse
a single set of BL images for other SoC/board without re-compiling TF-A
at all. This will also keep the code cleaner because it avoids #ifdef
around various base addresses.
By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really
position-independent now. You can load them anywhere irrespective of
their link address.
Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'docs/design/cpu-specific-build-macros.rst')
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