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| author | Roberto Vargas <roberto.vargas@arm.com> | 2018-08-13 14:17:43 +0100 |
|---|---|---|
| committer | Roberto Vargas <roberto.vargas@arm.com> | 2018-08-13 14:20:30 +0100 |
| commit | fcb52dbf16eaf509dbdc8c1c37c5b2bd819b0de5 (patch) | |
| tree | 097e408dd7978adb00931d146ef6db3fa8638495 /docs/cpu-specific-build-macros.rst | |
| parent | 6902e66a6b78d2a9f8c5dc745e10e385fb13067f (diff) | |
| download | platform_external_arm-trusted-firmware-fcb52dbf16eaf509dbdc8c1c37c5b2bd819b0de5.tar.gz platform_external_arm-trusted-firmware-fcb52dbf16eaf509dbdc8c1c37c5b2bd819b0de5.tar.bz2 platform_external_arm-trusted-firmware-fcb52dbf16eaf509dbdc8c1c37c5b2bd819b0de5.zip | |
cci: Use dsb to wait before reading status register
The CCI500 TRM explicitily requires completion of the write
operation before the read operation, and it is not guaranteed
by dmb but it is dsb.
Change-Id: Ieeaa0d1a4b8fcb87108dea9b6de03d9c8a150829
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Diffstat (limited to 'docs/cpu-specific-build-macros.rst')
0 files changed, 0 insertions, 0 deletions