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| author | android-build-team Robot <android-build-team-robot@google.com> | 2020-02-07 04:22:22 +0000 |
|---|---|---|
| committer | android-build-team Robot <android-build-team-robot@google.com> | 2020-02-07 04:22:22 +0000 |
| commit | d36ae3e4c44c6547467f7ca92298ebad99700cb3 (patch) | |
| tree | 76d9e0cabe45c1ed6d9ea87a5deb9c75c4345653 /docs/components/exception-handling.rst | |
| parent | f94bb7f616791b95961e9d25c0a7b0c79fd45edc (diff) | |
| parent | cabe6937f2c9d0a50e4631c0545bddd650233ae8 (diff) | |
| download | platform_external_arm-trusted-firmware-android11-gsi.tar.gz platform_external_arm-trusted-firmware-android11-gsi.tar.bz2 platform_external_arm-trusted-firmware-android11-gsi.zip | |
Snap for 6188643 from cabe6937f2c9d0a50e4631c0545bddd650233ae8 to rvc-releaseandroid-vts-11.0_r5android-vts-11.0_r4android-vts-11.0_r3android-vts-11.0_r2android-vts-11.0_r1android-security-11.0.0_r1android-platform-11.0.0_r9android-platform-11.0.0_r8android-platform-11.0.0_r7android-platform-11.0.0_r6android-platform-11.0.0_r5android-platform-11.0.0_r4android-platform-11.0.0_r3android-platform-11.0.0_r2android-platform-11.0.0_r10android-platform-11.0.0_r1android-cts-11.0_r5android-cts-11.0_r4android-cts-11.0_r3android-cts-11.0_r2android-cts-11.0_r1android-11.0.0_r5android-11.0.0_r4android-11.0.0_r3android-11.0.0_r25android-11.0.0_r2android-11.0.0_r17android-11.0.0_r1android11-tests-releaseandroid11-security-releaseandroid11-s1-releaseandroid11-releaseandroid11-platform-releaseandroid11-gsi
Change-Id: Id9d1eda28e2f504532858d4c602eeebec865f19e
Diffstat (limited to 'docs/components/exception-handling.rst')
| -rw-r--r-- | docs/components/exception-handling.rst | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/docs/components/exception-handling.rst b/docs/components/exception-handling.rst index 0d0173318..3f386854f 100644 --- a/docs/components/exception-handling.rst +++ b/docs/components/exception-handling.rst @@ -26,8 +26,8 @@ Introduction Through various control bits in the ``SCR_EL3`` register, the Arm architecture allows for asynchronous exceptions to be routed to EL3. As described in the -`Interrupt Framework Design`_ document, depending on the chosen interrupt -routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of +:ref:`Interrupt Management Framework` document, depending on the chosen +interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of ``SCR_EL3`` register to effect this routing. For most use cases, other than for the purpose of facilitating context switch between Normal and Secure worlds, FIQs and IRQs routed to EL3 are not required to be handled in EL3. @@ -143,8 +143,9 @@ Interrupt handling ------------------ The |EHF| is a client of *Interrupt Management Framework*, and registers the -top-level handler for interrupts that target EL3, as described in the `Interrupt -Framework Design`_ document. This has the following implications. +top-level handler for interrupts that target EL3, as described in the +:ref:`Interrupt Management Framework` document. This has the following +implications: - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of sufficient priority are signalled as FIQs, and therefore will be routed to @@ -618,9 +619,8 @@ The |EHF| has the following limitations: exception descriptor and the programmed priority of interrupts handled by the dispatcher match. The |EHF| cannot verify that this has been followed. ----- +-------------- -*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.* -.. _Interrupt Framework Design: ../design/interrupt-framework-design.rst .. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf |