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| author | Achin Gupta <achin.gupta@arm.com> | 2014-05-09 11:42:56 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-05-22 17:48:36 +0100 |
| commit | 6cf89021312a33395f804d80377a6ffdaadbbe21 (patch) | |
| tree | 48427615e67e18d94816112c216b6591f23b6be4 /bl32/tsp/tsp_main.c | |
| parent | fa9c08b7d117cb736911288668f9fd987505b4e3 (diff) | |
| download | platform_external_arm-trusted-firmware-6cf89021312a33395f804d80377a6ffdaadbbe21.tar.gz platform_external_arm-trusted-firmware-6cf89021312a33395f804d80377a6ffdaadbbe21.tar.bz2 platform_external_arm-trusted-firmware-6cf89021312a33395f804d80377a6ffdaadbbe21.zip | |
Add support for synchronous FIQ handling in TSP
This patch adds support in the TSP for handling S-EL1 interrupts
handed over by the TSPD. It includes GIC support in its platform port,
updates various statistics related to FIQ handling, exports an entry
point that the TSPD can use to hand over interrupts and defines the
handover protocol w.r.t what context is the TSP expected to preserve
and the state in which the entry point is invoked by the TSPD.
Change-Id: I93b22e5a8133400e4da366f5fc862f871038df39
Diffstat (limited to 'bl32/tsp/tsp_main.c')
| -rw-r--r-- | bl32/tsp/tsp_main.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index a7c738658..dff67d5ac 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c @@ -58,7 +58,7 @@ static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; /******************************************************************************* * Per cpu data structure to keep track of TSP activity ******************************************************************************/ -static work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; +work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; /******************************************************************************* * Single reference to the various entry points exported by the test secure @@ -71,6 +71,7 @@ static const entry_info_t tsp_entry_info = { tsp_cpu_off_entry, tsp_cpu_resume_entry, tsp_cpu_suspend_entry, + tsp_fiq_entry, }; |