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| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-16 11:08:14 +0800 |
|---|---|---|
| committer | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-19 10:56:31 +0800 |
| commit | 960a12b3fb4699cad83973c853fb5064ed6a75d0 (patch) | |
| tree | 6a33c0a28c429705fcc976f2addae8c758dc8098 /bl31 | |
| parent | d1b6013d8485094d948e6b6039b8d119a907ecf8 (diff) | |
| download | platform_external_arm-trusted-firmware-960a12b3fb4699cad83973c853fb5064ed6a75d0.tar.gz platform_external_arm-trusted-firmware-960a12b3fb4699cad83973c853fb5064ed6a75d0.tar.bz2 platform_external_arm-trusted-firmware-960a12b3fb4699cad83973c853fb5064ed6a75d0.zip | |
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
Diffstat (limited to 'bl31')
0 files changed, 0 insertions, 0 deletions