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| author | Achin Gupta <achin.gupta@arm.com> | 2014-08-04 23:13:10 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-08-15 10:21:50 +0100 |
| commit | 0c8d4fef28768233f1f46b4d085f904293dffd2c (patch) | |
| tree | f921b7d842ce3a7be0e7e701f35fbea187e8dee6 /bl31/aarch64/runtime_exceptions.S | |
| parent | c1efc4c0666b95912b54e079de484d8c2249e045 (diff) | |
| download | platform_external_arm-trusted-firmware-0c8d4fef28768233f1f46b4d085f904293dffd2c.tar.gz platform_external_arm-trusted-firmware-0c8d4fef28768233f1f46b4d085f904293dffd2c.tar.bz2 platform_external_arm-trusted-firmware-0c8d4fef28768233f1f46b4d085f904293dffd2c.zip | |
Unmask SError interrupt and clear SCR_EL3.EA bit
This patch disables routing of external aborts from lower exception levels to
EL3 and ensures that a SError interrupt generated as a result of execution in
EL3 is taken locally instead of a lower exception level.
The SError interrupt is enabled in the TSP code only when the operation has not
been directly initiated by the normal world. This is to prevent the possibility
of an asynchronous external abort which originated in normal world from being
taken when execution is in S-EL1.
Fixes ARM-software/tf-issues#153
Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
Diffstat (limited to 'bl31/aarch64/runtime_exceptions.S')
| -rw-r--r-- | bl31/aarch64/runtime_exceptions.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 996dedcb5..f5be9e077 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S @@ -44,6 +44,9 @@ * ----------------------------------------------------- */ .macro handle_sync_exception + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mrs x30, esr_el3 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH @@ -70,6 +73,9 @@ * ----------------------------------------------------- */ .macro handle_interrupt_exception label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] bl save_gp_registers |