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| author | Alistair Delva <adelva@google.com> | 2021-02-15 12:43:29 -0800 |
|---|---|---|
| committer | Alistair Delva <adelva@google.com> | 2021-02-15 12:44:34 -0800 |
| commit | faa476c0caaa598afa5a6109d17102db5fe35ec6 (patch) | |
| tree | 37a21c69306801ee7cdda5167a30896c8740155b /bl31/aarch64/bl31_entrypoint.S | |
| parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
| parent | 66306814586b1bf6bcb859aaad218ec3bb090e94 (diff) | |
| download | platform_external_arm-trusted-firmware-faa476c0caaa598afa5a6109d17102db5fe35ec6.tar.gz platform_external_arm-trusted-firmware-faa476c0caaa598afa5a6109d17102db5fe35ec6.tar.bz2 platform_external_arm-trusted-firmware-faa476c0caaa598afa5a6109d17102db5fe35ec6.zip | |
Merge branch 'aosp/upstream-master' into HEADandroid-s-preview-1
This keeps the bl31 interface change reverted which still has not been
fixed in upstream U-Boot for rockchip devices.
Test: CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rk3399 \
DEBUG=0 ERROR_DEPRECATED=1 bl31
Signed-off-by: Alistair Delva <adelva@google.com>
Change-Id: I7c3972a7b767715efb05593096d5d92dba14c609
Diffstat (limited to 'bl31/aarch64/bl31_entrypoint.S')
| -rw-r--r-- | bl31/aarch64/bl31_entrypoint.S | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 665a05e88..2d672dd12 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -110,13 +110,17 @@ func bl31_entrypoint * caches and participate in coherency. * -------------------------------------------------------------------- */ - adr x0, __DATA_START__ - adr x1, __DATA_END__ + adrp x0, __DATA_START__ + add x0, x0, :lo12:__DATA_START__ + adrp x1, __DATA_END__ + add x1, x1, :lo12:__DATA_END__ sub x1, x1, x0 bl clean_dcache_range - adr x0, __BSS_START__ - adr x1, __BSS_END__ + adrp x0, __BSS_START__ + add x0, x0, :lo12:__BSS_START__ + adrp x1, __BSS_END__ + add x1, x1, :lo12:__BSS_END__ sub x1, x1, x0 bl clean_dcache_range |