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| author | Alistair Delva <adelva@google.com> | 2021-02-16 21:01:22 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2021-02-16 21:01:22 +0000 |
| commit | efb2826bb8160e2d8e0fcec85133a7468484f9fd (patch) | |
| tree | 37a21c69306801ee7cdda5167a30896c8740155b /bl1/aarch32 | |
| parent | b00a71fc312c9781fa6f404dccfb55b062b2ccac (diff) | |
| parent | faa476c0caaa598afa5a6109d17102db5fe35ec6 (diff) | |
| download | platform_external_arm-trusted-firmware-master.tar.gz platform_external_arm-trusted-firmware-master.tar.bz2 platform_external_arm-trusted-firmware-master.zip | |
Merge branch 'aosp/upstream-master' into HEAD am: faa476c0caHEADandroid-s-beta-5android-s-beta-4android-s-beta-3android-s-beta-2android-s-beta-1mastermain-cg-testing-releaseandroid-s-beta-5android-s-beta-4
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1589611
MUST ONLY BE SUBMITTED BY AUTOMERGER
Change-Id: I3a25534ceed4f8e188510641080d8b8ed49b8f62
Diffstat (limited to 'bl1/aarch32')
| -rw-r--r-- | bl1/aarch32/bl1_context_mgmt.c | 20 | ||||
| -rw-r--r-- | bl1/aarch32/bl1_exceptions.S | 2 |
2 files changed, 11 insertions, 11 deletions
diff --git a/bl1/aarch32/bl1_context_mgmt.c b/bl1/aarch32/bl1_context_mgmt.c index b5a6a3417..85d35a72b 100644 --- a/bl1/aarch32/bl1_context_mgmt.c +++ b/bl1/aarch32/bl1_context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -53,10 +53,10 @@ void *cm_get_context(uint32_t security_state) return &bl1_cpu_context[security_state]; } -void cm_set_next_context(void *cpu_context) +void cm_set_next_context(void *context) { - assert(cpu_context); - bl1_next_cpu_context_ptr = cpu_context; + assert(context != NULL); + bl1_next_cpu_context_ptr = context; } void *cm_get_next_context(void) @@ -103,21 +103,21 @@ static void flush_smc_and_cpu_ctx(void) void bl1_prepare_next_image(unsigned int image_id) { unsigned int security_state, mode = MODE32_svc; - image_desc_t *image_desc; + image_desc_t *desc; entry_point_info_t *next_bl_ep; /* Get the image descriptor. */ - image_desc = bl1_plat_get_image_desc(image_id); - assert(image_desc); + desc = bl1_plat_get_image_desc(image_id); + assert(desc != NULL); /* Get the entry point info. */ - next_bl_ep = &image_desc->ep_info; + next_bl_ep = &desc->ep_info; /* Get the image security state. */ security_state = GET_SECURITY_STATE(next_bl_ep->h.attr); /* Prepare the SPSR for the next BL image. */ - if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()))) { + if ((security_state != SECURE) && (GET_VIRT_EXT(read_id_pfr1()) != 0U)) { mode = MODE32_hyp; } @@ -166,7 +166,7 @@ void bl1_prepare_next_image(unsigned int image_id) flush_smc_and_cpu_ctx(); /* Indicate that image is in execution state. */ - image_desc->state = IMAGE_STATE_EXECUTED; + desc->state = IMAGE_STATE_EXECUTED; print_entry_point_info(next_bl_ep); } diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index f2af9ab5b..493d2ca4e 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -80,7 +80,7 @@ debug_loop: add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET ldm r8, {r0, r1, r2, r3} - eret + exception_return endfunc bl1_aarch32_smc_handler /* ----------------------------------------------------- |