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| author | danh-arm <dan.handley@arm.com> | 2018-07-24 14:37:23 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-24 14:37:23 +0100 |
| commit | cffb00342897ed73a2bb9fc7a1860102bd927f2e (patch) | |
| tree | a5f4186122043f2b749b46f079dd35d5e16d8eac | |
| parent | 790e6c5b96c4c71958071702f5227bc4f47b3b2a (diff) | |
| parent | 6cb2a397032187b03fd7dbdf965f09b29f3594b1 (diff) | |
| download | platform_external_arm-trusted-firmware-cffb00342897ed73a2bb9fc7a1860102bd927f2e.tar.gz platform_external_arm-trusted-firmware-cffb00342897ed73a2bb9fc7a1860102bd927f2e.tar.bz2 platform_external_arm-trusted-firmware-cffb00342897ed73a2bb9fc7a1860102bd927f2e.zip | |
Merge pull request #1488 from b49020/integration
synquacer: Enable optional OP-TEE support
| -rw-r--r-- | plat/socionext/synquacer/platform.mk | 4 | ||||
| -rw-r--r-- | plat/socionext/synquacer/sq_bl31_setup.c | 35 |
2 files changed, 28 insertions, 11 deletions
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk index 546f84aa1..96427a161 100644 --- a/plat/socionext/synquacer/platform.mk +++ b/plat/socionext/synquacer/platform.mk @@ -18,6 +18,10 @@ ERRATA_A53_855873 := 1 # Libraries include lib/xlat_tables_v2/xlat_tables.mk +ifeq (${SPD},opteed) +TF_CFLAGS_aarch64 += -DBL32_BASE=0xfc000000 +endif + PLAT_PATH := plat/socionext/synquacer PLAT_INCLUDES := -I$(PLAT_PATH)/include \ -I$(PLAT_PATH)/drivers/scpi \ diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index 461c8dece..30d06e9eb 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -70,15 +70,31 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, assert(from_bl2 == NULL); assert(plat_params_from_bl2 == NULL); + /* Initialize power controller before setting up topology */ + plat_sq_pwrc_setup(); + #ifdef BL32_BASE - /* Populate entry point information for BL32 */ - SET_PARAM_HEAD(&bl32_image_ep_info, - PARAM_EP, - VERSION_1, - 0); - SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + struct draminfo di = {0}; + + scpi_get_draminfo(&di); + + /* + * Check if OP-TEE has been loaded in Secure RAM allocated + * from DRAM1 region + */ + if ((di.base1 + di.size1) <= BL32_BASE) { + NOTICE("OP-TEE has been loaded by SCP firmware\n"); + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); + } else { + NOTICE("OP-TEE has not been loaded by SCP firmware\n"); + } #endif /* BL32_BASE */ /* Populate entry point information for BL33 */ @@ -125,9 +141,6 @@ void bl31_platform_setup(void) /* Allow access to the System counter timer module */ sq_configure_sys_timer(); - - /* Initialize power controller before setting up topology */ - plat_sq_pwrc_setup(); } void bl31_plat_runtime_setup(void) |