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| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-20 15:33:27 +0800 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2019-09-12 12:36:31 +0000 |
| commit | b90f207a1d386ec391bd3ea9eb403c4ad7b7551b (patch) | |
| tree | e7e7acdda3c1a7823b8ba8d7f14fe3f27bc1d64f | |
| parent | 2fc6ffc451c9af16e03eff51e779c33828e9ab07 (diff) | |
| download | platform_external_arm-trusted-firmware-b90f207a1d386ec391bd3ea9eb403c4ad7b7551b.tar.gz platform_external_arm-trusted-firmware-b90f207a1d386ec391bd3ea9eb403c4ad7b7551b.tar.bz2 platform_external_arm-trusted-firmware-b90f207a1d386ec391bd3ea9eb403c4ad7b7551b.zip | |
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | docs/getting_started/user-guide.rst | 6 | ||||
| -rw-r--r-- | include/arch/aarch64/el3_common_macros.S | 2 | ||||
| -rw-r--r-- | make_helpers/defaults.mk | 3 | ||||
| -rw-r--r-- | plat/intel/soc/agilex/platform.mk | 1 |
5 files changed, 13 insertions, 1 deletions
@@ -689,6 +689,7 @@ $(eval $(call assert_boolean,USE_TBBR_DEFS)) $(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call assert_boolean,BL2_AT_EL3)) $(eval $(call assert_boolean,BL2_IN_XIP_MEM)) +$(eval $(call assert_boolean,BL2_INV_DCACHE)) $(eval $(call assert_numeric,ARM_ARCH_MAJOR)) $(eval $(call assert_numeric,ARM_ARCH_MINOR)) @@ -749,6 +750,7 @@ $(eval $(call add_define,USE_TBBR_DEFS)) $(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY)) $(eval $(call add_define,BL2_AT_EL3)) $(eval $(call add_define,BL2_IN_XIP_MEM)) +$(eval $(call add_define,BL2_INV_DCACHE)) ifeq (${SANITIZE_UB},trap) $(eval $(call add_define,MONITOR_TRAPS)) diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst index 48cbdb9f4..3828d0b4e 100644 --- a/docs/getting_started/user-guide.rst +++ b/docs/getting_started/user-guide.rst @@ -287,6 +287,12 @@ Common build options enable this use-case. For now, this option is only supported when BL2_AT_EL3 is set to '1'. +- ``BL2_INV_DCACHE``: This is an optional build option which control dcache + invalidation upon BL2 entry. Some platform cannot handle cache operations + during entry as the coherency unit is not yet initialized. This may cause + crashing. Leaving this option to '1' (default) will allow the operation. + This option is only relevant when BL2_AT_EL3 is set to '1'. + - ``BL31``: This is an optional build option which specifies the path to BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built. diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index a36b7da79..53396d44b 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -333,7 +333,7 @@ * --------------------------------------------------------------------- */ .if \_init_c_runtime -#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3) +#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE) /* ------------------------------------------------------------- * Invalidate the RW memory used by the BL31 image. This * includes the data and NOBITS sections. This is done to diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index e462505a2..b6f76559c 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -33,6 +33,9 @@ BL2_AT_EL3 := 0 # when BL2_AT_EL3 is 1. BL2_IN_XIP_MEM := 0 +# Do dcache invalidate upon BL2 entry at EL3 +BL2_INV_DCACHE := 1 + # Select the branch protection features to use. BRANCH_PROTECTION := 0 diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 5d20462b7..d1ea62915 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -70,5 +70,6 @@ BL31_SOURCES += \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 +BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 USE_COHERENT_MEM := 1 |