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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-01-04 09:13:32 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-04 09:13:32 +0000 |
| commit | acfc1bc259045f30c625c5abba24195c87ac1c89 (patch) | |
| tree | 90cb44d6f2694a00718940cede1d8f7fc57efb28 | |
| parent | c8765826f4c2d10db0b660defccc84f7bce11af0 (diff) | |
| parent | 65849aa595fa0fad1e9b9fd13c24d5b756e61aa6 (diff) | |
| download | platform_external_arm-trusted-firmware-acfc1bc259045f30c625c5abba24195c87ac1c89.tar.gz platform_external_arm-trusted-firmware-acfc1bc259045f30c625c5abba24195c87ac1c89.tar.bz2 platform_external_arm-trusted-firmware-acfc1bc259045f30c625c5abba24195c87ac1c89.zip | |
Merge pull request #1728 from satheesbalya-arm/sb1/sb1_2497_v84_dit
Enable DIT if supported
| -rw-r--r-- | include/common/aarch32/el3_common_macros.S | 12 | ||||
| -rw-r--r-- | include/common/aarch64/el3_common_macros.S | 12 | ||||
| -rw-r--r-- | include/lib/aarch32/arch.h | 9 | ||||
| -rw-r--r-- | include/lib/aarch64/arch.h | 14 |
4 files changed, 44 insertions, 3 deletions
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index 243842320..048f16103 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -110,6 +110,18 @@ stcopr r0, SDCR #endif + /* + * If Data Independent Timing (DIT) functionality is implemented, + * always enable DIT in EL3 + */ + ldcopr r0, ID_PFR0 + and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT) + cmp r0, #ID_PFR0_DIT_SUPPORTED + bne 1f + mrs r0, cpsr + orr r0, r0, #CPSR_DIT_BIT + msr cpsr_cxsf, r0 +1: .endm /* ----------------------------------------------------------------------------- diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S index 008daca9e..410aeab75 100644 --- a/include/common/aarch64/el3_common_macros.S +++ b/include/common/aarch64/el3_common_macros.S @@ -130,6 +130,18 @@ */ mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) msr cptr_el3, x0 + + /* + * If Data Independent Timing (DIT) functionality is implemented, + * always enable DIT in EL3 + */ + mrs x0, id_aa64pfr0_el1 + ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH + cmp x0, #ID_AA64PFR0_DIT_SUPPORTED + bne 1f + mov x0, #DIT_BIT + msr DIT, x0 +1: .endm /* ----------------------------------------------------------------------------- diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index fa6e5dbdd..8260c5491 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -94,11 +94,17 @@ /* CSSELR definitions */ #define LEVEL_SHIFT U(1) -/* ID_PFR0 definitions */ +/* ID_PFR0 AMU definitions */ #define ID_PFR0_AMU_SHIFT U(20) #define ID_PFR0_AMU_LENGTH U(4) #define ID_PFR0_AMU_MASK U(0xf) +/* ID_PFR0 DIT definitions */ +#define ID_PFR0_DIT_SHIFT U(24) +#define ID_PFR0_DIT_LENGTH U(4) +#define ID_PFR0_DIT_MASK U(0xf) +#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) + /* ID_PFR1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT U(12) #define ID_PFR1_VIRTEXT_MASK U(0xf) @@ -276,6 +282,7 @@ #define DISABLE_ALL_EXCEPTIONS \ (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) +#define CPSR_DIT_BIT (U(1) << 21) /* * TTBCR definitions */ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 6f81e1b41..72a14dcfa 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -135,6 +135,10 @@ #define ID_AA64PFR0_SVE_LENGTH U(4) #define ID_AA64PFR0_MPAM_SHIFT U(40) #define ID_AA64PFR0_MPAM_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_SHIFT U(48) +#define ID_AA64PFR0_DIT_MASK ULL(0xf) +#define ID_AA64PFR0_DIT_LENGTH U(4) +#define ID_AA64PFR0_DIT_SUPPORTED U(1) #define ID_AA64PFR0_CSV2_SHIFT U(56) #define ID_AA64PFR0_CSV2_MASK ULL(0xf) #define ID_AA64PFR0_CSV2_LENGTH U(4) @@ -778,7 +782,7 @@ /******************************************************************************* * RAS system registers - *******************************************************************************/ + ******************************************************************************/ #define DISR_EL1 S3_0_C12_C1_1 #define DISR_A_BIT U(31) @@ -807,7 +811,13 @@ /******************************************************************************* * Armv8.3 Pointer Authentication Registers - *******************************************************************************/ + ******************************************************************************/ #define APGAKeyLo_EL1 S3_0_C2_C3_0 +/******************************************************************************* + * Armv8.4 Data Independent Timing Registers + ******************************************************************************/ +#define DIT S3_3_C4_C2_5 +#define DIT_BIT BIT(24) + #endif /* ARCH_H */ |