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| author | Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> | 2020-09-22 12:47:33 +0100 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2020-10-20 20:07:06 +0000 |
| commit | a3ecbb3553564d8e560209fdde165c85129b3f70 (patch) | |
| tree | ee0fcdd6112123cdebf78d244624e82b568aec3e | |
| parent | d32113c7f3d291b35e0debdccac609c88a0343ae (diff) | |
| download | platform_external_arm-trusted-firmware-a3ecbb3553564d8e560209fdde165c85129b3f70.tar.gz platform_external_arm-trusted-firmware-a3ecbb3553564d8e560209fdde165c85129b3f70.tar.bz2 platform_external_arm-trusted-firmware-a3ecbb3553564d8e560209fdde165c85129b3f70.zip | |
plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts
Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
| -rw-r--r-- | fdts/tc0.dts | 2 | ||||
| -rw-r--r-- | plat/arm/board/tc0/include/platform_def.h | 35 | ||||
| -rw-r--r-- | plat/arm/board/tc0/tc0_plat.c | 2 |
3 files changed, 37 insertions, 2 deletions
diff --git a/fdts/tc0.dts b/fdts/tc0.dts index 15c14cabd..763c813cf 100644 --- a/fdts/tc0.dts +++ b/fdts/tc0.dts @@ -106,7 +106,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; + reg = <0x0 0x80000000 0x0 0x7d000000>; }; psci { diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h index 075c4037b..81b3944e5 100644 --- a/plat/arm/board/tc0/include/platform_def.h +++ b/plat/arm/board/tc0/include/platform_def.h @@ -22,6 +22,41 @@ #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ /* + * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, + * its base is ARM_AP_TZC_DRAM1_BASE. + * + * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for: + * - BL32_BASE when SPD_spmd is enabled + * - Region to load Trusted OS + */ +#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ + TC0_TZC_DRAM1_SIZE) +#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ +#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \ + TC0_TZC_DRAM1_SIZE - 1) + +#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE +#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE - \ + TC0_TZC_DRAM1_SIZE) +#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \ + TC0_NS_DRAM1_SIZE - 1) + +/* + * Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure) + */ +#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + TC0_NS_DRAM1_BASE, \ + TC0_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + + +#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ + TC0_TZC_DRAM1_BASE, \ + TC0_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. */ diff --git a/plat/arm/board/tc0/tc0_plat.c b/plat/arm/board/tc0/tc0_plat.c index 05461928d..304666a01 100644 --- a/plat/arm/board/tc0/tc0_plat.c +++ b/plat/arm/board/tc0/tc0_plat.c @@ -38,7 +38,7 @@ const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, TC0_FLASH0_RO, TC0_MAP_DEVICE, - ARM_MAP_NS_DRAM1, + TC0_MAP_NS_DRAM1, #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif |