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| author | André Przywara <andre.przywara@arm.com> | 2020-07-07 22:06:31 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-07-07 22:06:31 +0000 |
| commit | 99c447f4406c8ae66b6cab2341ef0c8e8d9751d2 (patch) | |
| tree | 8506a671c4d6fa7e5978c5f82610c44a7bfbf2a6 | |
| parent | 33172350908fb183f6b467cedab9d0b88b0f9267 (diff) | |
| parent | 8e570b71d8773bcf220253e39d48f1fa00ec4aaa (diff) | |
| download | platform_external_arm-trusted-firmware-99c447f4406c8ae66b6cab2341ef0c8e8d9751d2.tar.gz platform_external_arm-trusted-firmware-99c447f4406c8ae66b6cab2341ef0c8e8d9751d2.tar.bz2 platform_external_arm-trusted-firmware-99c447f4406c8ae66b6cab2341ef0c8e8d9751d2.zip | |
Merge "drivers: arm: gicv3: auto-detect presence of GIC600-AE" into integration
| -rw-r--r-- | drivers/arm/gic/v3/gic-x00.c | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/drivers/arm/gic/v3/gic-x00.c b/drivers/arm/gic/v3/gic-x00.c index c1a9f0dc1..cc9717451 100644 --- a/drivers/arm/gic/v3/gic-x00.c +++ b/drivers/arm/gic/v3/gic-x00.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,26 +21,27 @@ #include "gicv3_private.h" /* GIC-600 specific register offsets */ -#define GICR_PWRR 0x24 -#define IIDR_MODEL_ARM_GIC_600 0x0200043b +#define GICR_PWRR 0x24 +#define IIDR_MODEL_ARM_GIC_600 (0x0200043b) +#define IIDR_MODEL_ARM_GIC_600AE (0x0300043b) /* GICR_PWRR fields */ -#define PWRR_RDPD_SHIFT 0 -#define PWRR_RDAG_SHIFT 1 -#define PWRR_RDGPD_SHIFT 2 -#define PWRR_RDGPO_SHIFT 3 +#define PWRR_RDPD_SHIFT 0 +#define PWRR_RDAG_SHIFT 1 +#define PWRR_RDGPD_SHIFT 2 +#define PWRR_RDGPO_SHIFT 3 -#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT) -#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT) -#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT) -#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT) +#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT) +#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT) +#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT) +#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT) /* * Values to write to GICR_PWRR register to power redistributor * for operating through the core (GICR_PWRR.RDAG = 0) */ -#define PWRR_ON (0 << PWRR_RDPD_SHIFT) -#define PWRR_OFF (1 << PWRR_RDPD_SHIFT) +#define PWRR_ON (0 << PWRR_RDPD_SHIFT) +#define PWRR_OFF (1 << PWRR_RDPD_SHIFT) #if GICV3_SUPPORT_GIC600 @@ -115,7 +117,8 @@ static bool gicv3_is_gic600(uintptr_t gicr_base) { uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR); - return (reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600; + return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) || + ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE)); } #endif |