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| author | Andrew F. Davis <afd@ti.com> | 2018-10-12 15:37:04 -0500 |
|---|---|---|
| committer | Andrew F. Davis <afd@ti.com> | 2018-10-16 09:27:53 -0500 |
| commit | 6a655a85c09a6a1707b40993d261fbafc1f511c5 (patch) | |
| tree | bce49023409f39f2632205a722058b5fdd3e9756 | |
| parent | 0a09313ec780d2f66efcda3eb2a5d1632719bd81 (diff) | |
| download | platform_external_arm-trusted-firmware-6a655a85c09a6a1707b40993d261fbafc1f511c5.tar.gz platform_external_arm-trusted-firmware-6a655a85c09a6a1707b40993d261fbafc1f511c5.tar.bz2 platform_external_arm-trusted-firmware-6a655a85c09a6a1707b40993d261fbafc1f511c5.zip | |
ti: k3: common: Do not disable cache on TI K3 core powerdown
Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.
Signed-off-by: Andrew F. Davis <afd@ti.com>
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 4 | ||||
| -rw-r--r-- | plat/ti/k3/common/k3_psci.c | 12 | ||||
| -rw-r--r-- | plat/ti/k3/common/plat_common.mk | 6 |
3 files changed, 21 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 3a23e025f..108509f1f 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -228,11 +228,13 @@ endfunc cortex_a53_reset_func func cortex_a53_core_pwr_dwn mov x18, x30 +#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache +#endif /* --------------------------------------------- * Flush L1 caches. @@ -252,11 +254,13 @@ endfunc cortex_a53_core_pwr_dwn func cortex_a53_cluster_pwr_dwn mov x18, x30 +#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache +#endif /* --------------------------------------------- * Flush L1 caches. diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c index e75ebac8c..787cc82fd 100644 --- a/plat/ti/k3/common/k3_psci.c +++ b/plat/ti/k3/common/k3_psci.c @@ -6,9 +6,12 @@ #include <arch_helpers.h> #include <assert.h> +#include <cpu_data.h> #include <debug.h> #include <k3_gicv3.h> #include <psci.h> +/* Need to flush psci internal locks before shutdown or their values are lost */ +#include <../../lib/psci/psci_private.h> #include <platform.h> #include <stdbool.h> @@ -99,6 +102,14 @@ void k3_pwr_domain_on_finish(const psci_power_state_t *target_state) k3_gic_cpuif_enable(); } +static void __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t + *target_state) +{ + flush_cpu_data(psci_svc_cpu_data); + flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks)); + psci_power_down_wfi(); +} + static void __dead2 k3_system_reset(void) { /* Send the system reset request to system firmware */ @@ -128,6 +139,7 @@ static const plat_psci_ops_t k3_plat_psci_ops = { .pwr_domain_on = k3_pwr_domain_on, .pwr_domain_off = k3_pwr_domain_off, .pwr_domain_on_finish = k3_pwr_domain_on_finish, + .pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi, .system_reset = k3_system_reset, .validate_power_state = k3_validate_power_state, .validate_ns_entrypoint = k3_validate_ns_entrypoint diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index 31481785d..d8354368d 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -12,7 +12,7 @@ COLD_BOOT_SINGLE_CPU := 1 PROGRAMMABLE_RESET_ADDRESS:= 1 # System coherency is managed in hardware -WARMBOOT_ENABLE_DCACHE_EARLY:= 1 +HW_ASSISTED_COHERENCY := 1 USE_COHERENT_MEM := 0 # A53 erratum for SoC. (enable them all) @@ -22,6 +22,10 @@ ERRATA_A53_836870 := 1 ERRATA_A53_843419 := 1 ERRATA_A53_855873 := 1 +# Leave the caches enabled on core powerdown path +TI_AM65X_WORKAROUND := 1 +$(eval $(call add_define,TI_AM65X_WORKAROUND)) + MULTI_CONSOLE_API := 1 TI_16550_MDR_QUIRK := 1 $(eval $(call add_define,TI_16550_MDR_QUIRK)) |