diff options
| author | Ying-Chun Liu (PaulLiu) <paulliu@debian.org> | 2019-01-22 03:27:55 +0800 |
|---|---|---|
| committer | Ying-Chun Liu (PaulLiu) <paulliu@debian.org> | 2019-01-26 00:13:49 +0800 |
| commit | 2be86dd3954a5a3bd5111c3861a74c1f8a592884 (patch) | |
| tree | d8bf03ee4e6a6bcf5e61a53a2e05ad6e547e04a8 | |
| parent | d604ac483136d8d611264474a5e57c31632f46ca (diff) | |
| download | platform_external_arm-trusted-firmware-2be86dd3954a5a3bd5111c3861a74c1f8a592884.tar.gz platform_external_arm-trusted-firmware-2be86dd3954a5a3bd5111c3861a74c1f8a592884.tar.bz2 platform_external_arm-trusted-firmware-2be86dd3954a5a3bd5111c3861a74c1f8a592884.zip | |
rpi3: Enable GPIO in BL2
This patch inits the GPIO in BL2 earlysetup. So BL2 can start operating
GPIO pins.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
| -rw-r--r-- | plat/rpi3/platform.mk | 4 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_bl2_setup.c | 19 | ||||
| -rw-r--r-- | plat/rpi3/rpi3_hw.h | 6 |
3 files changed, 29 insertions, 0 deletions
diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk index 5e76345a5..ded92bd3d 100644 --- a/plat/rpi3/platform.mk +++ b/plat/rpi3/platform.mk @@ -27,6 +27,10 @@ BL2_SOURCES += common/desc_image_load.c \ drivers/io/io_fip.c \ drivers/io/io_memmap.c \ drivers/io/io_storage.c \ + drivers/gpio/gpio.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/rpi3/gpio/rpi3_gpio.c \ plat/common/aarch64/platform_mp_stack.S \ plat/rpi3/aarch64/plat_helpers.S \ plat/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \ diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c index 53a2c72b8..09f056212 100644 --- a/plat/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi3/rpi3_bl2_setup.c @@ -15,12 +15,25 @@ #include <lib/optee_utils.h> #include <lib/xlat_tables/xlat_mmu_helpers.h> #include <lib/xlat_tables/xlat_tables_defs.h> +#include <drivers/generic_delay_timer.h> +#include <drivers/rpi3/gpio/rpi3_gpio.h> #include "rpi3_private.h" /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); +/* rpi3 GPIO setup function. */ +static void rpi3_gpio_setup(void) +{ + struct rpi3_gpio_params params; + + memset(¶ms, 0, sizeof(struct rpi3_gpio_params)); + params.reg_base = RPI3_GPIO_BASE; + + rpi3_gpio_init(¶ms); +} + /******************************************************************************* * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted SRAM. @@ -35,6 +48,12 @@ void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, /* Initialize the console to provide early debug support */ rpi3_console_init(); + /* Enable arch timer */ + generic_delay_timer_init(); + + /* Setup GPIO driver */ + rpi3_gpio_setup(); + /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; diff --git a/plat/rpi3/rpi3_hw.h b/plat/rpi3/rpi3_hw.h index 9d86eb880..61d183772 100644 --- a/plat/rpi3/rpi3_hw.h +++ b/plat/rpi3/rpi3_hw.h @@ -84,6 +84,12 @@ #define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) /* + * GPIO controller + */ +#define RPI3_IO_GPIO_OFFSET ULL(0x00200000) +#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) + +/* * Local interrupt controller */ #define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) |