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| author | Charulatha V <charu@ti.com> | 2011-06-03 23:31:58 +0530 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2011-07-14 11:53:41 -0700 |
| commit | 16fef5c05c2f1eee93546842c6d8377c2a1134cd (patch) | |
| tree | e4a06890b22ba194c434078f48df4f37cbf7031e /drivers/gpio | |
| parent | 9877cd098e03484d483beb481170cda014423662 (diff) | |
| download | kernel_samsung_tuna-16fef5c05c2f1eee93546842c6d8377c2a1134cd.tar.gz kernel_samsung_tuna-16fef5c05c2f1eee93546842c6d8377c2a1134cd.tar.bz2 kernel_samsung_tuna-16fef5c05c2f1eee93546842c6d8377c2a1134cd.zip | |
GPIO: OMAP: Fix use of readl/readw to access isr_reg
In gpio_irq_handler, isr register is always accessed as 32 bit register and only
for OMAP15xx the first 16 MSBs are masked. Correct this by using the appropriate
readl/readw registers as per the bank width.
Signed-off-by: Charulatha V <charu@ti.com>
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/gpio-omap.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 7d578e8e486..90a107a31ee 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -583,10 +583,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) u32 enabled; enabled = _get_gpio_irqbank_mask(bank); - isr_saved = isr = __raw_readl(isr_reg) & enabled; - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) - isr &= 0x0000ffff; + if (bank->width == 32) + isr = __raw_readl(isr_reg) & enabled; + else if (bank->width == 16) + isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff; + isr_saved = isr; if (bank->regs->leveldetect0) level_mask = bank->level_mask & enabled; |