diff options
Diffstat (limited to 'libpixelflinger/codeflinger/GGLAssembler.cpp')
| -rw-r--r-- | libpixelflinger/codeflinger/GGLAssembler.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/libpixelflinger/codeflinger/GGLAssembler.cpp b/libpixelflinger/codeflinger/GGLAssembler.cpp index 325caba8a..346779f47 100644 --- a/libpixelflinger/codeflinger/GGLAssembler.cpp +++ b/libpixelflinger/codeflinger/GGLAssembler.cpp @@ -893,7 +893,8 @@ void GGLAssembler::build_and_immediate(int d, int s, uint32_t mask, int bits) return; } - if (getCodegenArch() == CODEGEN_ARCH_MIPS) { + if ((getCodegenArch() == CODEGEN_ARCH_MIPS) || + (getCodegenArch() == CODEGEN_ARCH_MIPS64)) { // MIPS can do 16-bit imm in 1 instr, 32-bit in 3 instr // the below ' while (mask)' code is buggy on mips // since mips returns true on isValidImmediate() @@ -1057,7 +1058,8 @@ RegisterAllocator::RegisterFile& RegisterAllocator::registerFile() RegisterAllocator::RegisterFile::RegisterFile(int codegen_arch) : mRegs(0), mTouched(0), mStatus(0), mArch(codegen_arch), mRegisterOffset(0) { - if (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) { + if ((mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) || + (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS64)) { mRegisterOffset = 2; // ARM has regs 0..15, MIPS offset to 2..17 } reserve(ARMAssemblerInterface::SP); @@ -1067,7 +1069,8 @@ RegisterAllocator::RegisterFile::RegisterFile(int codegen_arch) RegisterAllocator::RegisterFile::RegisterFile(const RegisterFile& rhs, int codegen_arch) : mRegs(rhs.mRegs), mTouched(rhs.mTouched), mArch(codegen_arch), mRegisterOffset(0) { - if (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) { + if ((mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS) || + (mArch == ARMAssemblerInterface::CODEGEN_ARCH_MIPS64)) { mRegisterOffset = 2; // ARM has regs 0..15, MIPS offset to 2..17 } } |