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authorHenrik Smiding <henrik.smiding@intel.com>2014-01-15 16:12:02 +0100
committerWang LiangX <liangx.wang@intel.com>2014-04-18 11:31:54 +0800
commitc27a444e54d531f8a0cd33e67dc46ff7c763cc4b (patch)
treef93e108d398788c0b25572c673d14e0f230b4f52 /libcutils/arch-x86
parenta740b3bb409c9acdf4cf6a829b982e57a89d08de (diff)
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Add Silvermont architecture cache sizes
Adds Silvermont specific cache sizes for memset16/32 SSE optimization. Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70 Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
Diffstat (limited to 'libcutils/arch-x86')
-rw-r--r--libcutils/arch-x86/cache_wrapper.S11
1 files changed, 9 insertions, 2 deletions
diff --git a/libcutils/arch-x86/cache_wrapper.S b/libcutils/arch-x86/cache_wrapper.S
index 508fdd3e2..9eee25c69 100644
--- a/libcutils/arch-x86/cache_wrapper.S
+++ b/libcutils/arch-x86/cache_wrapper.S
@@ -17,8 +17,15 @@
* Contributed by: Intel Corporation
*/
+#if defined(__slm__)
+/* Values are optimized for Silvermont */
+#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */
+#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */
+#else
/* Values are optimized for Atom */
-#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
-#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
+#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */
+#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */
+#endif
+
#define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2)
#define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2)