aboutsummaryrefslogtreecommitdiffstats
path: root/cpu/microblaze/irq.S
blob: 393d6e8dd42a32950174b6980ae510977cfb874a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
/*
 * (C) Copyright 2007 Michal Simek
 *
 * Michal  SIMEK <monstr@monstr.eu>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
	.text
	.global _interrupt_handler
_interrupt_handler:
	addi	r1, r1, -4
	swi	r2, r1, 0
	addi	r1, r1, -4
	swi	r3, r1, 0
	addi	r1, r1, -4
	swi	r4, r1, 0
	addi	r1, r1, -4
	swi	r5, r1, 0
	addi	r1, r1, -4
	swi	r6, r1, 0
	addi	r1, r1, -4
	swi	r7, r1, 0
	addi	r1, r1, -4
	swi	r8, r1, 0
	addi	r1, r1, -4
	swi	r9, r1, 0
	addi	r1, r1, -4
	swi	r10, r1, 0
	addi	r1, r1, -4
	swi	r11, r1, 0
	addi	r1, r1, -4
	swi	r12, r1, 0
	addi	r1, r1, -4
	swi	r13, r1, 0
	addi	r1, r1, -4
	swi	r14, r1, 0
	addi	r1, r1, -4
	swi	r15, r1, 0
	addi	r1, r1, -4
	swi	r16, r1, 0
	addi	r1, r1, -4
	swi	r17, r1, 0
	addi	r1, r1, -4
	swi	r18, r1, 0
	addi	r1, r1, -4
	swi	r19, r1, 0
	addi	r1, r1, -4
	swi	r20, r1, 0
	addi	r1, r1, -4
	swi	r21, r1, 0
	addi	r1, r1, -4
	swi	r22, r1, 0
	addi	r1, r1, -4
	swi	r23, r1, 0
	addi	r1, r1, -4
	swi	r24, r1, 0
	addi	r1, r1, -4
	swi	r25, r1, 0
	addi	r1, r1, -4
	swi	r26, r1, 0
	addi	r1, r1, -4
	swi	r27, r1, 0
	addi	r1, r1, -4
	swi	r28, r1, 0
	addi	r1, r1, -4
	swi	r29, r1, 0
	addi	r1, r1, -4
	swi	r30, r1, 0
	addi	r1, r1, -4
	swi	r31, r1, 0
	brlid	r15, interrupt_handler
	nop
	nop
	lwi	r31, r1, 0
	addi	r1, r1, 4
	lwi	r30, r1, 0
	addi	r1, r1, 4
	lwi	r29, r1, 0
	addi	r1, r1, 4
	lwi	r28, r1, 0
	addi	r1, r1, 4
	lwi	r27, r1, 0
	addi	r1, r1, 4
	lwi	r26, r1, 0
	addi	r1, r1, 4
	lwi	r25, r1, 0
	addi	r1, r1, 4
	lwi	r24, r1, 0
	addi	r1, r1, 4
	lwi	r23, r1, 0
	addi	r1, r1, 4
	lwi	r22, r1, 0
	addi	r1, r1, 4
	lwi	r21, r1, 0
	addi	r1, r1, 4
	lwi	r20, r1, 0
	addi	r1, r1, 4
	lwi	r19, r1, 0
	addi	r1, r1, 4
	lwi	r18, r1, 0
	addi	r1, r1, 4
	lwi	r17, r1, 0
	addi	r1, r1, 4
	lwi	r16, r1, 0
	addi	r1, r1, 4
	lwi	r15, r1, 0
	addi	r1, r1, 4
	lwi	r14, r1, 0
	addi	r1, r1, 4
	lwi	r13, r1, 0
	addi	r1, r1, 4
	lwi	r12, r1, 0
	addi	r1, r1, 4
	lwi	r11, r1, 0
	addi	r1, r1, 4
	lwi	r10, r1, 0
	addi	r1, r1, 4
	lwi	r9, r1, 0
	addi	r1, r1, 4
	lwi	r8, r1, 0
	addi	r1, r1, 4
	lwi	r7, r1, 0
	addi	r1, r1, 4
	lwi	r6, r1, 0
	addi	r1, r1, 4
	lwi	r5, r1, 0
	addi	r1, r1, 4
	lwi	r4, r1, 0
	addi	r1, r1, 4
	lwi	r3, r1, 0
	addi	r1, r1, 4
	lwi	r2, r1, 0
	addi	r1, r1, 4

	/* enable_interrupt */
	msrset	r0, 2
	bra	r14
	nop
	nop
	.size _interrupt_handler,.-_interrupt_handler