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-rw-r--r--cpu/mpc8xx/fec.c2
-rw-r--r--cpu/mpc8xx/serial.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index 141425d8ed..89c1ff939d 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -398,7 +398,7 @@ static void fec_pin_init(int fecidx)
* * the MII management interface clock must be less than or equal
* * to 2.5 MHz.
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
- * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
+ * * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
*
* All MII configuration is done via FEC1 registers:
*/
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index cae90ddaf5..bd90dcd3b0 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -70,7 +70,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp)
int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
if(divisor/16>0x1000) {
- /* bad divisor, assume 50Mhz clock and 9600 baud */
+ /* bad divisor, assume 50MHz clock and 9600 baud */
divisor=(50*1000*1000 + 8*9600)/16/9600;
}