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-rw-r--r--cpu/arm926ejs/davinci/lowlevel_init.S79
-rw-r--r--cpu/arm926ejs/davinci/nand.c41
-rw-r--r--cpu/arm926ejs/davinci/timer.c69
3 files changed, 111 insertions, 78 deletions
diff --git a/cpu/arm926ejs/davinci/lowlevel_init.S b/cpu/arm926ejs/davinci/lowlevel_init.S
index 79bc692c14..a87c112eca 100644
--- a/cpu/arm926ejs/davinci/lowlevel_init.S
+++ b/cpu/arm926ejs/davinci/lowlevel_init.S
@@ -3,11 +3,6 @@
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
- * Copyright (C) 2008 Prodrive BV <pv@prodrive.nl>
- * Changed:
- * Made board specific defines such as DDR timing and PLL
- * dividers. These should be set in the board config file
- *
* Partially based on TI sources, original copyrights follow:
*/
@@ -161,17 +156,17 @@ WaitPPL2Loop:
/* Program the PLL Multiplier */
ldr r6, PLL2_PLLM
- mov r2, $CFG_DAVINCI_PLL2_PLLM
+ mov r2, $0x17 /* 162 MHz */
str r2, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV2
- mov r3, $CFG_DAVINCI_PLL2_DIV2
+ mov r3, $0x01
str r3, [r6]
/* Program the PLL2 Divisor Value */
ldr r6, PLL2_DIV1
- mov r4, $CFG_DAVINCI_PLL2_DIV1
+ mov r4, $0x0b /* 54 MHz */
str r4, [r6]
/* PLL2 DIV2 MMR */
@@ -278,7 +273,7 @@ checkDDRStatClkStop:
bne checkDDRStatClkStop
/*------------------------------------------------------*
- * Program DDR2 MMRs *
+ * Program DDR2 MMRs for 162MHz Setting *
*------------------------------------------------------*/
/* Program PHY Control Register */
@@ -293,12 +288,12 @@ checkDDRStatClkStop:
/* Program SDRAM TIM-0 Config Register */
ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL
+ ldr r7, SDTIM0_VAL_162MHz
str r7, [r6]
/* Program SDRAM TIM-1 Config Register */
ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL
+ ldr r7, SDTIM1_VAL_162MHz
str r7, [r6]
/* Program the SDRAM Bank Config Control Register */
@@ -440,7 +435,7 @@ WaitLoop:
/* Program the PLL Multiplier */
ldr r6, PLL1_PLLM
- mov r3, $CFG_DAVINCI_PLL1_PLLM
+ mov r3, $0x15 /* For 594MHz */
str r3, [r6]
/* Wait for PLL to Reset Properly */
@@ -472,7 +467,7 @@ PLL1Lock:
nop
/*------------------------------------------------------*
- * AEMIF configuration for NAND/NOR Flash *
+ * AEMIF configuration for NOR Flash (double check) *
*------------------------------------------------------*/
ldr r0, _PINMUX0
ldr r1, _DEV_SETTING
@@ -484,12 +479,6 @@ PLL1Lock:
orr r2, r2, r1
str r2, [r0]
- ldr r0, ACFG2
- ldr r1, ACFG2_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
ldr r0, ACFG3
ldr r1, ACFG3_VAL
ldr r2, [r0]
@@ -508,12 +497,6 @@ PLL1Lock:
and r1, r2, r1
str r1, [r0]
- ldr r0, NANDFCR
- ldr r1, NANDFCR_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
/*--------------------------------------*
* VTP manual Calibration *
*--------------------------------------*/
@@ -577,36 +560,24 @@ _PINMUX1:
.word 0x01c40004 /* Device Configuration Registers */
_DEV_SETTING:
- .word CFG_DAVINCI_PINMUX_0
+ .word 0x00000c1f
WAITCFG:
.word 0x01e00004
WAITCFG_VAL:
- .word CFG_DAVINCI_WAITCFG
-ACFG2:
- .word 0x01e00010
-ACFG2_VAL:
- .word CFG_DAVINCI_ACFG2
+ .word 0
ACFG3:
.word 0x01e00014
ACFG3_VAL:
- .word CFG_DAVINCI_ACFG3
+ .word 0x3ffffffd
ACFG4:
.word 0x01e00018
ACFG4_VAL:
- .word CFG_DAVINCI_ACFG4
+ .word 0x3ffffffd
ACFG5:
.word 0x01e0001c
ACFG5_VAL:
- .word CFG_DAVINCI_ACFG5
-NANDFCR:
- .word 0x01e00060
-NANDFCR_VAL:
-#ifdef CFG_DAVINCI_NANDCE
- .word (1 << (CFG_DAVINCI_NANDCE - 2))
-#else
- .word 0x00000000
-#endif
+ .word 0x3ffffffd
MDCTL_DDR2:
.word 0x01c41a34
@@ -628,27 +599,33 @@ PSC_FLAG_CLEAR:
PSC_GEM_FLAG_CLEAR:
.word 0xfffffeff
-/* DDR2 MMR & CONFIGURATION VALUES */
+/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
DDRCTL:
.word 0x200000e4
DDRCTL_VAL:
- .word CFG_DAVINCI_DDRCTL
+ .word 0x50006405
SDREF:
.word 0x2000000c
SDREF_VAL:
- .word CFG_DAVINCI_SDREF
+ .word 0x000005c3
SDCFG:
.word 0x20000008
SDCFG_VAL:
- .word CFG_DAVINCI_SDCFG
+#ifdef DDR_4BANKS
+ .word 0x00178622
+#elif defined DDR_8BANKS
+ .word 0x00178632
+#else
+#error "Unknown DDR configuration!!!"
+#endif
SDTIM0:
.word 0x20000010
-SDTIM0_VAL:
- .word CFG_DAVINCI_SDTIM0
+SDTIM0_VAL_162MHz:
+ .word 0x28923211
SDTIM1:
.word 0x20000014
-SDTIM1_VAL:
- .word CFG_DAVINCI_SDTIM1
+SDTIM1_VAL_162MHz:
+ .word 0x0016c722
VTPIOCR:
.word 0x200000f0 /* VTP IO Control register */
DDRVTPR:
@@ -722,7 +699,7 @@ PLL2_DIV_MASK:
MMARG_BRF0:
.word 0x01c42010 /* BRF margin mode 0 (R/W)*/
MMARG_BRF0_VAL:
- .word CFG_DAVINCI_MMARG_BRF0
+ .word 0x00444400
DDR2_START_ADDR:
.word 0x80000000
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 3257f83a2f..127be9fcd4 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
dummy = emif_addr->NANDF3ECC;
dummy = emif_addr->NANDF4ECC;
- emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6));
+ emif_addr->NANDFCR |= (1 << 8);
}
static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
@@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
- region = (CFG_DAVINCI_NANDCE - 1);
+ region = 1;
while (n--) {
tmp = nand_davinci_readecc(mtd, region);
*ecc_code++ = tmp;
@@ -311,9 +311,40 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i
static void nand_flash_init(void)
{
- /* All EMIF initialization is done in lowlevel_init.S
- * and config values are in the board config files
- */
+ u_int32_t acfg1 = 0x3ffffffc;
+ u_int32_t acfg2 = 0x3ffffffc;
+ u_int32_t acfg3 = 0x3ffffffc;
+ u_int32_t acfg4 = 0x3ffffffc;
+ emifregs emif_regs;
+
+ /*------------------------------------------------------------------*
+ * NAND FLASH CHIP TIMEOUT @ 459 MHz *
+ * *
+ * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
+ * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
+ * *
+ *------------------------------------------------------------------*/
+ acfg1 = 0
+ | (0 << 31 ) /* selectStrobe */
+ | (0 << 30 ) /* extWait */
+ | (1 << 26 ) /* writeSetup 10 ns */
+ | (3 << 20 ) /* writeStrobe 40 ns */
+ | (1 << 17 ) /* writeHold 10 ns */
+ | (1 << 13 ) /* readSetup 10 ns */
+ | (5 << 7 ) /* readStrobe 60 ns */
+ | (1 << 4 ) /* readHold 10 ns */
+ | (3 << 2 ) /* turnAround ?? ns */
+ | (0 << 0 ) /* asyncSize 8-bit bus */
+ ;
+
+ emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
+
+ emif_regs->AWCCR |= 0x10000000;
+ emif_regs->AB1CR = acfg1; /* 0x08244128 */;
+ emif_regs->AB2CR = acfg2;
+ emif_regs->AB3CR = acfg3;
+ emif_regs->AB4CR = acfg4;
+ emif_regs->NANDFCR = 0x00000101;
}
int board_nand_init(struct nand_chip *nand)
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 4797797b6d..8bb8b45713 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -42,9 +42,9 @@
typedef volatile struct {
u_int32_t pid12;
- u_int32_t emumgt;
- u_int32_t na1;
- u_int32_t na2;
+ u_int32_t emumgt_clksped;
+ u_int32_t gpint_en;
+ u_int32_t gpdir_dat;
u_int32_t tim12;
u_int32_t tim34;
u_int32_t prd12;
@@ -52,12 +52,21 @@ typedef volatile struct {
u_int32_t tcr;
u_int32_t tgcr;
u_int32_t wdtcr;
+ u_int32_t tlgc;
+ u_int32_t tlmr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
-#define TIM_CLK_DIV 16
+#define READ_TIMER timer->tim34
+
+/*
+ * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap
+ * around of timestamp already after min ~159s, divide it, e.g. by 16.
+ * timestamp will then wrap around all min ~42min
+ */
+#define DIV(x) ((x) >> 4)
static ulong timestamp;
static ulong lastinc;
@@ -67,50 +76,63 @@ int timer_init(void)
/* We are using timer34 in unchained 32-bit mode, full speed */
timer->tcr = 0x0;
timer->tgcr = 0x0;
- timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8);
+ timer->tgcr = 0x06;
timer->tim34 = 0x0;
timer->prd34 = TIMER_LOAD_VAL;
lastinc = 0;
+ timer->tcr = 0x80 << 16;
timestamp = 0;
- timer->tcr = 2 << 22;
return(0);
}
void reset_timer(void)
{
- timer->tcr = 0x0;
- timer->tim34 = 0;
- lastinc = 0;
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return(get_timer_masked() - base);
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+void reset_timer_masked(void)
+{
+ lastinc = DIV(READ_TIMER);
timestamp = 0;
- timer->tcr = 2 << 22;
}
-static ulong get_timer_raw(void)
+ulong get_timer_raw(void)
{
- ulong now = timer->tim34;
+ ulong now = DIV(READ_TIMER);
if (now >= lastinc) {
/* normal mode */
timestamp += now - lastinc;
} else {
/* overflow ... */
- timestamp += now + TIMER_LOAD_VAL - lastinc;
+ timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc;
}
lastinc = now;
return timestamp;
}
-ulong get_timer(ulong base)
-{
- return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); }
-
-void set_timer(ulong t)
+ulong get_timer_masked(void)
{
- timestamp = t;
+ return(get_timer_raw() / DIV(TIMER_LOAD_VAL));
}
-void udelay(unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -118,7 +140,7 @@ void udelay(unsigned long usec)
tmo = CFG_HZ_CLOCK / 1000;
tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
+ tmo /= 1000;
endtime = get_timer_raw() + tmo;
@@ -143,5 +165,8 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
- return CFG_HZ;
+ ulong tbclk;
+
+ tbclk = CFG_HZ;
+ return(tbclk);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 23:25:28 +0000