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| author | Stefan Roese <sr@denx.de> | 2008-01-09 10:28:20 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-09 10:28:20 +0100 |
| commit | 8f24e0637ae113500d8bd60d80d57afcc0aa8bde (patch) | |
| tree | 4f17b423e33303a05b883cfede86c1b42714283b /include | |
| parent | 1754f50b710194f886b6f2831803d8960171a14d (diff) | |
| download | u-boot-midas-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.tar.gz u-boot-midas-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.tar.bz2 u-boot-midas-8f24e0637ae113500d8bd60d80d57afcc0aa8bde.zip | |
ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/lwmon5.h | 19 | ||||
| -rw-r--r-- | include/ppc440.h | 4 |
2 files changed, 13 insertions, 10 deletions
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 5210024d8f..0bf536b6b5 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -71,15 +71,20 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ -#define CFG_OCM_DATA_ADDR CFG_OCM_BASE - +/* + * On LWMON5 we use D-cache as init-ram and stack pointer. We also move + * the POST_WORD from OCM to a 440EPx register that preserves it's + * content during reset (GPT0_COM6). This way we reserve the OCM (16k) + * for logbuffer only. + */ +#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) + /* unused GPT0 COMP reg */ /*----------------------------------------------------------------------- * Serial Port diff --git a/include/ppc440.h b/include/ppc440.h index 90e56b0989..b0d16fb4a7 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1354,8 +1354,6 @@ #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ @@ -1421,7 +1419,7 @@ #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ -#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ +#define GPT0_COMP6 0x00000098 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_USB2D0CR 0x0320 |