diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2009-02-07 05:41:17 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-03-23 15:14:53 -0400 |
| commit | 58130f8920151d9e8942bbdf3388f2defb47e415 (patch) | |
| tree | 9beacb3a8a2e28d5259acb7eb8c89b9529f30555 /include | |
| parent | 820b076c449688bcd4af6db5a33ae424d1a60d0e (diff) | |
| download | u-boot-midas-58130f8920151d9e8942bbdf3388f2defb47e415.tar.gz u-boot-midas-58130f8920151d9e8942bbdf3388f2defb47e415.tar.bz2 u-boot-midas-58130f8920151d9e8942bbdf3388f2defb47e415.zip | |
Blackfin: drop SPORT_TX read helper macros
The SPORT_TX registers cannot be read (the hardware will trigger an error),
so drop the read helper macros.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'include')
9 files changed, 0 insertions, 26 deletions
diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h index 85acdd6cf7..dec7c63bad 100644 --- a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h +++ b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h @@ -304,7 +304,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) @@ -370,7 +369,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h index b9e4d67702..58df301617 100644 --- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h +++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h @@ -304,7 +304,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) @@ -370,7 +369,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h index e9572a0b00..51d9cf240a 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF542-extended_cdef.h @@ -3577,7 +3577,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -3643,7 +3642,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -3709,7 +3707,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h index 968cd3eb3a..4c0fdf52bf 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended_cdef.h @@ -4678,7 +4678,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -4744,7 +4743,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -4810,7 +4808,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h index bd40f356e8..e0f76ae1ef 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF547-extended_cdef.h @@ -2713,7 +2713,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -2779,7 +2778,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -2845,7 +2843,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -2911,7 +2908,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h index 77cd5dc779..caf2f6fb6d 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF548-extended_cdef.h @@ -4885,7 +4885,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -4951,7 +4950,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -5017,7 +5015,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -5083,7 +5080,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h index c5d3511b0b..af90e4c62e 100644 --- a/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h +++ b/include/asm-blackfin/mach-bf548/ADSP-EDN-BF549-extended_cdef.h @@ -5233,7 +5233,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -5299,7 +5298,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) @@ -5365,7 +5363,6 @@ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) #define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ -#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) #define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) @@ -5431,7 +5428,6 @@ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) #define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ -#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) #define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h index c0c7e1e28b..43f385021d 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h @@ -1798,7 +1798,6 @@ #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) #define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) @@ -1861,7 +1860,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h index fde25c0ed9..2e61b5faae 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h @@ -1039,7 +1039,6 @@ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) #define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) #define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) @@ -1081,7 +1080,6 @@ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) #define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) #define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) |