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| author | Marek Vasut <marex@denx.de> | 2015-08-19 07:46:49 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-23 11:56:21 +0200 |
| commit | 29aa439759ed2e5dfa45cd8d6d5a1d51604e3820 (patch) | |
| tree | bfda5c57dc97c8c8f49849e572ef649ebaa2b1f5 /include/rc4.h | |
| parent | 9238b52abd788cf4c2311896a5ada34ecff5499c (diff) | |
| download | u-boot-midas-29aa439759ed2e5dfa45cd8d6d5a1d51604e3820.tar.gz u-boot-midas-29aa439759ed2e5dfa45cd8d6d5a1d51604e3820.tar.bz2 u-boot-midas-29aa439759ed2e5dfa45cd8d6d5a1d51604e3820.zip | |
arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'include/rc4.h')
0 files changed, 0 insertions, 0 deletions