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| author | Praveen Rao <prao@ti.com> | 2015-03-09 17:12:06 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-13 09:29:01 -0400 |
| commit | 5f603761c3de00423cad405e064cd2fc822feab1 (patch) | |
| tree | b4a5ed5a564c806d6fbee7f8f93e87cae55f81d2 /include/configs/ti_omap5_common.h | |
| parent | 49ec9490918909c9694b8ee64789f1eed335df1b (diff) | |
| download | u-boot-midas-5f603761c3de00423cad405e064cd2fc822feab1.tar.gz u-boot-midas-5f603761c3de00423cad405e064cd2fc822feab1.tar.bz2 u-boot-midas-5f603761c3de00423cad405e064cd2fc822feab1.zip | |
ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
This patch enables the workaround for ARM errata 798870 for OMAP5 /
DRA7 which says "If back-to-back speculative cache line fills (fill
A and fill B) are issued from the L1 data cache of a CPU to the
L2 cache, the second request (fill B) is then cancelled, and the
second request would have detected a hazard against a recent write or
eviction (write B) to the same cache line as fill B then the L2 logic
might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
here as well.
Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/ti_omap5_common.h')
| -rw-r--r-- | include/configs/ti_omap5_common.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 925cb42dd3..09f05f18a7 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -21,6 +21,9 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_798870 + #define CONFIG_SYS_CACHELINE_SIZE 64 /* Use General purpose timer 1 */ |