aboutsummaryrefslogtreecommitdiffstats
path: root/include/configs/incaip.h
diff options
context:
space:
mode:
authorwdenk <wdenk>2003-07-31 22:56:30 +0000
committerwdenk <wdenk>2003-07-31 22:56:30 +0000
commit96dd9af4c7c5669924c2e40734b246f207b9a8b4 (patch)
tree375c20dc2ca61a2c8a9bf9dd373ecc2882c2a102 /include/configs/incaip.h
parent1f4bb37d6bcae59b18a2438f3cdca6545a831ab5 (diff)
downloadu-boot-midas-96dd9af4c7c5669924c2e40734b246f207b9a8b4.tar.gz
u-boot-midas-96dd9af4c7c5669924c2e40734b246f207b9a8b4.tar.bz2
u-boot-midas-96dd9af4c7c5669924c2e40734b246f207b9a8b4.zip
Must enable timebase earlier on MPC5200
Diffstat (limited to 'include/configs/incaip.h')
-rw-r--r--include/configs/incaip.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 027f319828..b17d7f34e8 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -32,7 +32,7 @@
#define CONFIG_INCA_IP 1 /* on a INCA-IP Board */
/* allowed values: 100000000, 133000000, and 150000000 */
-#define CPU_CLOCK_RATE 133000000 /* 133 MHz clock for the MIPS core */
+#define CPU_CLOCK_RATE 133000000 /* 133 MHz clock for the MIPS core */
#if CPU_CLOCK_RATE == 100000000
#define INFINEON_EBU_BOOTCFG 0x20C4 /* CMULT = 4 for 100 MHz */