rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 122 insertions, 122 deletions

diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 60df12fcea..239ff67330 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -48,7 +48,7 @@
 #undef	CONFIG_CONS_NONE		/* It's not on external UART */
 #define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
 
-#define CFG_BCSR		0xFA000000
+#define CONFIG_SYS_BCSR		0xFA000000
 
 /*
  * Select ethernet configuration
@@ -70,13 +70,13 @@
 #define CONFIG_ETHER_ON_FCC2
 #define CONFIG_ETHER_ON_FCC3
 
-#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
-#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 
-#define CFG_CPMFCR_RAMTYPE	0
-#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
 
 #define CONFIG_MII			/* MII PHY management        */
 #define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
@@ -85,15 +85,15 @@
  * GPIO pins used for bit-banged MII communications
  */
 #define MDIO_PORT		0	/* Not used - implemented in BCSR */
-#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
-#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
 
-#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
-				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
 
-#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
-				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
 
 #define MIIDELAY		udelay(1)
 
@@ -104,7 +104,7 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
 
 
 /*
@@ -162,27 +162,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define CFG_LONGHELP			/* undef to save memory	    */
-#define CFG_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
 #else
-#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
 
-#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
 
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 /*-----------------------------------------------------------------------
  * Environment
@@ -200,27 +200,27 @@
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#define CFG_FLASH_BASE		0xFC000000
-#define CFG_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
-#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000
-#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
 /*-----------------------------------------------------------------------
  * I2C
  *----------------------------------------------------------------------*/
 /* EEPROM Configuration */
-#define CFG_EEPROM_SIZE	0x1000
-#define CFG_I2C_EEPROM_ADDR	0x54
-#define CFG_I2C_EEPROM_ADDR_LEN	1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_EEPROM_SIZE	0x1000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
 
 #ifdef CONFIG_ENV_IS_IN_EEPROM
 #define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
@@ -229,22 +229,22 @@
 
 /* RTC Configuration */
 #define CONFIG_RTC_M41T11	1	/* uses a M41T81 */
-#define CFG_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #define CONFIG_M41T11_BASE_YEAR	1900
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75		1
 #define CONFIG_DTT_SENSORS	{0}
-#define CFG_DTT_MAX_TEMP	70
-#define CFG_DTT_LOW_TEMP	-30
-#define	CFG_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define	CONFIG_SYS_DTT_HYSTERESIS	3
 
 /*-----------------------------------------------------------------------
  * NVRAM Configuration
  *-----------------------------------------------------------------------
  */
-#define CFG_NVRAM_BASE_ADDR	0xFA080000
-#define CFG_NVRAM_SIZE		(128*1024)-16
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFA080000
+#define CONFIG_SYS_NVRAM_SIZE		(128*1024)-16
 
 
 /*-----------------------------------------------------------------------
@@ -258,9 +258,9 @@
 #define CONFIG_PCI_BOOTDELAY	0
 
 /* PCI Memory map (if different from default map */
-#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define CFG_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
-#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
 				 PICMR_PREFETCH_EN)
 
 /*
@@ -276,11 +276,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
-#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
-#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
-#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
 /*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -288,11 +288,11 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
-#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
-#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
-#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
-#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 
 /*
  * Master window that allows the CPU to access PCI IO space.
@@ -300,105 +300,105 @@
  * in the bridge.
  */
 
-#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
-#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
-#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
-#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
-#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
 
 
 /* PCIBR0 - for PCI IO*/
-#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
-#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		CONFIG_SYS_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
 /* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
-#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCIMSK1_MASK		~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
 
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #if defined(CONFIG_CMD_JFFS2)
-#define CFG_JFFS2_FIRST_BANK	0
-#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
-#define CFG_JFFS2_FIRST_SECTOR  0
-#define CFG_JFFS2_LAST_SECTOR   62
-#define CFG_JFFS2_SORT_FRAGMENTS
-#define CFG_JFFS_CUSTOM_PART
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
+#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS_CUSTOM_PART
 #endif
 
 #if defined(CONFIG_CMD_I2C)
 #define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
-#define CFG_I2C_SPEED		100000	/* I2C speed			*/
-#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
 #endif
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #endif
 
-#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
 
-#define CFG_DEFAULT_IMMR	0x00010000
-#define CFG_IMMR		0xF0000000
+#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
+#define CONFIG_SYS_IMMR		0xF0000000
 
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 
 /* Hard reset configuration word */
-#define CFG_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
+#define CONFIG_SYS_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
 /* No slaves */
-#define CFG_HRCW_SLAVE1		0
-#define CFG_HRCW_SLAVE2		0
-#define CFG_HRCW_SLAVE3		0
-#define CFG_HRCW_SLAVE4		0
-#define CFG_HRCW_SLAVE5		0
-#define CFG_HRCW_SLAVE6		0
-#define CFG_HRCW_SLAVE7		0
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot                  */
 
-#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
-#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		0
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
 
-#define CFG_HID2		0
+#define CONFIG_SYS_HID2		0
 
-#define CFG_SIUMCR		0x02610000
-#define CFG_SYPCR		0xFFFF0689
-#define CFG_BCR			0x8080E000
-#define CFG_SCCR		0x00000001
+#define CONFIG_SYS_SIUMCR		0x02610000
+#define CONFIG_SYS_SYPCR		0xFFFF0689
+#define CONFIG_SYS_BCR			0x8080E000
+#define CONFIG_SYS_SCCR		0x00000001
 
-#define CFG_RMR			0
-#define CFG_TMCNTSC		0x000000C3
-#define CFG_PISCR		0x00000083
-#define CFG_RCCR		0
+#define CONFIG_SYS_RMR			0
+#define CONFIG_SYS_TMCNTSC		0x000000C3
+#define CONFIG_SYS_PISCR		0x00000083
+#define CONFIG_SYS_RCCR		0
 
-#define CFG_MPTPR		0x0A00
-#define CFG_PSDMR		0xC432246E
-#define CFG_PSRT		0x32
+#define CONFIG_SYS_MPTPR		0x0A00
+#define CONFIG_SYS_PSDMR		0xC432246E
+#define CONFIG_SYS_PSRT		0x32
 
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
-#define CFG_SDRAM_OR		0xF0002900
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_SDRAM_OR		0xF0002900
 
-#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
-#define CFG_OR0_PRELIM		0xFC000882
-#define CFG_BR4_PRELIM		(CFG_BCSR | 0x00001001)
-#define CFG_OR4_PRELIM		0xFFF00050
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFC000882
+#define CONFIG_SYS_BR4_PRELIM		(CONFIG_SYS_BCSR | 0x00001001)
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00050
 
-#define CFG_RESET_ADDRESS	0xFFF00100
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
 
 #endif /* __CONFIG_H */