* Cleanup lowboot code for MPC5200

* Minor code cleanup (coding style)

* Patch by Reinhard Meyer, 30 Dec 2003:
  - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
  - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
  - turned debug print of PHY registers into a function (called in two places)
  - added support for EMK MPC5200 based modules

* Fix MPC8xx PLPRCR_MFD_SHIFT typo

* Add support for TQM866M modules

* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)

* Fix a few compiler warnings

1 files changed, 96 insertions, 64 deletions

diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 21daa2d971..624beed31a 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -1,16 +1,17 @@
 /*
  * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.

- *

- * modified for TOP5200 by Reinhard Meyer, www.emk-elektronik.de

- * TOP5200 differences from IceCube:

- * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks

- *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins

- * 1 SDRAM/DDRAM Bank up to 256 MB

- * local VPD I2C Bus is software driven and uses

- *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL

- * FLASH is located at 0x80000000

- * Internal regs are at 0xfff00000

+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
+ *
+ * TOP5200 differences from IceCube:
+ * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
+ *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
+ * 1 SDRAM/DDRAM Bank up to 256 MB
+ * local VPD I2C Bus is software driven and uses
+ *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
+ * FLASH is re-located at 0xff000000
+ * Internal regs are at 0xf0000000
  * Reset jumps to 0x00000100
  *
  * See file CREDITS for list of people who contributed to this
@@ -44,7 +45,7 @@
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
 
-#define CFG_MPC5XXX_CLKIN	33333333 /* ... running at 33MHz */
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -98,17 +99,48 @@
 #include <cmd_confdefs.h>
 
 /*
+ * low boot
+ */
+#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+
+/*
  * Autobooting
  */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
 
 /*
  * IPB Bus clocking configuration.
  */
 #undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
-

+
 /*
  * I2C configuration
  */
@@ -120,21 +152,21 @@
 
 #define CFG_I2C_EEPROM_ADDR_LEN 2
 #define CFG_EEPROM_SIZE 0x2000
-

+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_MISC_INIT_R
-

+
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support */
 #define	CONFIG_SOFT_I2C		1
-

+
 #if defined (CONFIG_SOFT_I2C)
 #  define SDA0			0x40
 #  define SCL0			0x80
-#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))

-#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))

-#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))

-#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))

-#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))

+#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
+#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
+#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
+#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
+#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
 #  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
 #  define I2C_READ		((DVI0&SDA0)?1:0)
 #  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
@@ -145,12 +177,12 @@
 #  define CFG_I2C_SPEED		100000
 #  define CFG_I2C_SLAVE		0x7F
 #endif
-

-#if defined (CONFIG_HARD_I2C)

+
+#if defined (CONFIG_HARD_I2C)
 #  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
 #  define CFG_I2C_SPEED		100000	/* 100 kHz */
 #  define CFG_I2C_SLAVE		0x7F
-#endif

+#endif
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
@@ -158,7 +190,7 @@
 #define CFG_FLASH_BASE		0xff000000
 #define CFG_FLASH_SIZE		0x01000000
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0)

+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0)
 
 #define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
@@ -167,32 +199,32 @@
 
 #undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
 
-/*

- * DRAM configuration - will be read from VPD later... TODO!

- */

-#if 0

-/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */

-#define	CFG_DRAM_DDR		0

-#define CFG_DRAM_EMODE		0

-#define CFG_DRAM_MODE		0x008D

-#define CFG_DRAM_CONTROL	0x514F0000

-#define CFG_DRAM_CONFIG1	0xC2233A00

-#define CFG_DRAM_CONFIG2	0x88B70004

-#define	CFG_DRAM_TAP_DEL	0x08

-#define CFG_DRAM_RAM_SIZE	0x19

-#endif

-#if 1

-/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */

-#define	CFG_DRAM_DDR		0

-#define CFG_DRAM_EMODE		0

-#define CFG_DRAM_MODE		0x00CD

-#define CFG_DRAM_CONTROL	0x514F0000

-#define CFG_DRAM_CONFIG1	0xD2333A00

-#define CFG_DRAM_CONFIG2	0x8AD70004

-#define	CFG_DRAM_TAP_DEL	0x08

-#define CFG_DRAM_RAM_SIZE	0x19

-#endif

-

+/*
+ * DRAM configuration - will be read from VPD later... TODO!
+ */
+#if 0
+/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
+#define	CFG_DRAM_DDR		0
+#define CFG_DRAM_EMODE		0
+#define CFG_DRAM_MODE		0x008D
+#define CFG_DRAM_CONTROL	0x514F0000
+#define CFG_DRAM_CONFIG1	0xC2233A00
+#define CFG_DRAM_CONFIG2	0x88B70004
+#define	CFG_DRAM_TAP_DEL	0x08
+#define CFG_DRAM_RAM_SIZE	0x19
+#endif
+#if 1
+/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
+#define	CFG_DRAM_DDR		0
+#define CFG_DRAM_EMODE		0
+#define CFG_DRAM_MODE		0x00CD
+#define CFG_DRAM_CONTROL	0x514F0000
+#define CFG_DRAM_CONFIG1	0xD2333A00
+#define CFG_DRAM_CONFIG2	0x8AD70004
+#define	CFG_DRAM_TAP_DEL	0x08
+#define CFG_DRAM_RAM_SIZE	0x19
+#endif
+
 /*
  * Environment settings
  */
@@ -201,17 +233,17 @@
 #define CFG_ENV_SIZE		0x0700
 #define CFG_I2C_EEPROM_ADDR 0x57
 
-/*

- * VPD settings

- */

+/*
+ * VPD settings
+ */
 #define CFG_FACT_OFFSET		0x1800
 #define CFG_FACT_SIZE		0x0800
 #define CFG_I2C_FACT_ADDR	0x57
-

+
 /*
- * Memory map

- *

- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000

+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
  */
 #define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
 #define CFG_SDRAM_BASE		0x00000000
@@ -240,12 +272,12 @@
  */
 #define CONFIG_MPC5XXX_FEC	1
 #define CONFIG_FEC_10MBIT	1		/* Workaround for FEC 100Mbit problem */
-#define	CONFIG_PHY_ADDR		0x1f

+#define	CONFIG_PHY_ADDR		0x1f
 #define	CONFIG_PHY_TYPE		0x79c874
 /*
- * GPIO configuration:

- * PSC1,2,3 predefined as UART

- * PCI disabled

+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
  * Ethernet 100 with MD
  */
 #define CFG_GPS_PORT_CONFIG	0x00058444