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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2016-05-16 15:31:37 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-11-15 15:28:00 +0100 |
| commit | 27183d7c22c35f648474e646171997eaef83947b (patch) | |
| tree | 0fafc7c6eff95b11844f35ba9e0b3341665eb914 /drivers | |
| parent | 02bcff2c56ed1528c01bf718892e0b4dc37dfacc (diff) | |
| download | u-boot-midas-27183d7c22c35f648474e646171997eaef83947b.tar.gz u-boot-midas-27183d7c22c35f648474e646171997eaef83947b.tar.bz2 u-boot-midas-27183d7c22c35f648474e646171997eaef83947b.zip | |
net: zynq_gem: Modify the nwcfg bit definitions
Modify the nwcfg bit definitions to have 32-bit
by removing the extra nibble.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/zynq_gem.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 8b7c1be5d9..0023b1689e 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -53,16 +53,16 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ -#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ -#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ -#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ -#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ -#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ +#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ +#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ +#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x80000000 /* SGMII Enable */ +#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ #ifdef CONFIG_ARM64 -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ #else -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ #endif #ifdef CONFIG_ARM64 |