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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-16 21:30:44 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-16 21:30:44 +0200 |
| commit | dc39ae9513c32dfeb9e018dc0d22c6484514fefb (patch) | |
| tree | 136c61b2c9731ddf51ef3e222bbf1e44781c5175 /drivers/spi | |
| parent | f75a729b5c1434d5a5bbf453b1b699bf1c3ffbce (diff) | |
| download | u-boot-midas-dc39ae9513c32dfeb9e018dc0d22c6484514fefb.tar.gz u-boot-midas-dc39ae9513c32dfeb9e018dc0d22c6484514fefb.tar.bz2 u-boot-midas-dc39ae9513c32dfeb9e018dc0d22c6484514fefb.zip | |
at91sam9/at91cap: improve clock framework
calculate dynamically the clock rate and pllb setting for usb
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/atmel_dataflash_spi.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 3eb252c5b5..614965c367 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <asm/arch/at91_pio.h> @@ -45,7 +46,7 @@ void AT91F_SpiInit(void) writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(0)); #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 @@ -53,7 +54,7 @@ void AT91F_SpiInit(void) writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(1)); #endif @@ -62,7 +63,7 @@ void AT91F_SpiInit(void) writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(3)); #endif |