Fix LOWBOOT configuration for MPC5200 with DDR memory

2 files changed, 23 insertions, 22 deletions

diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index a1631f49a4..559c7f415a 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -108,18 +108,19 @@ boot_warm:
 #error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
 #endif /* CFG_RAMBOOT */
 	lis	r4, CFG_DEFAULT_MBAR@h
-	lis	r3,     0x0000FF00@h
-	ori	r3, r3, 0x0000FF00@l
-	stw	r3, 0x4(r4)
-	lis	r3,     0x0000FFFF@h
-	ori	r3, r3, 0x0000FFFF@l
-	stw	r3, 0x8(r4)
+	lis	r3,	START_REG(CFG_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+	stw	r3, 0x4(r4)		/* CS0 start */
+	lis	r3,	STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+
+	stw	r3, 0x8(r4)		/* CS0 stop */
 	lis	r3,     0x00047800@h
 	ori	r3, r3, 0x00047800@l
-	stw	r3, 0x300(r4)
+	stw	r3, 0x300(r4)		/* set timing, CS0/boot conf reg */
 	lis	r3,     0x02010000@h
 	ori	r3, r3, 0x02010000@l
-	stw	r3, 0x54(r4)
+	stw	r3, 0x54(r4)		/* CS0 and Boot enable, IPBI ctrl reg */
 
 	lis     r3,	lowboot_reentry@h
 	ori     r3, r3, lowboot_reentry@l
@@ -127,18 +128,18 @@ boot_warm:
 	blr				/* jump to flash based address */
 
 lowboot_reentry:
-	lis	r3,     0x0000FF00@h
-	ori	r3, r3, 0x0000FF00@l
-	stw	r3, 0x4c(r4)
-	lis	r3,     0x0000FFFF@h
-	ori	r3, r3, 0x0000FFFF@l
-	stw	r3, 0x50(r4)
+	lis	r3,	START_REG(CFG_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CFG_BOOTCS_START)@l
+	stw	r3, 0x4c(r4)		/* Boot start */
+	lis	r3,	STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CFG_BOOTCS_START, CFG_BOOTCS_SIZE)@l
+	stw	r3, 0x50(r4)		/* Boot stop */
 	lis	r3,     0x00047800@h
 	ori	r3, r3, 0x00047800@l
-	stw	r3, 0x300(r4)
+	stw	r3, 0x300(r4)		/* set timing, CS0/boot conf reg */
 	lis	r3,     0x02000001@h
 	ori	r3, r3, 0x02000001@l
-	stw	r3, 0x54(r4)
+	stw	r3, 0x54(r4)		/* Boot enable, CS0 disable, wait state enable */
 #endif	/* CFG_LOWBOOT */
 
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c
index 5b5eac2084..5fcb376c13 100644
--- a/cpu/mpc5xxx/usb_ohci.c
+++ b/cpu/mpc5xxx/usb_ohci.c
@@ -488,7 +488,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
 		if (ohci->ed_controltail == NULL) {
 			writel (ed, &ohci->regs->ed_controlhead);
 		} else {
-			ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 (ed);
+			ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
 		}
 		ed->ed_prev = ohci->ed_controltail;
 		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
@@ -504,7 +504,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
 		if (ohci->ed_bulktail == NULL) {
 			writel (ed, &ohci->regs->ed_bulkhead);
 		} else {
-			ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 (ed);
+			ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
 		}
 		ed->ed_prev = ohci->ed_bulktail;
 		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
@@ -598,7 +598,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
 		ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
 		/* dummy td; end of td list for ed */
 		td = td_alloc (usb_dev);
-		ed->hwTailP = ohci_cpu_to_le32 (td);
+		ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
 		ed->hwHeadP = ed->hwTailP;
 		ed->state = ED_UNLINK;
 		ed->type = usb_pipetype (pipe);
@@ -656,12 +656,12 @@ static void td_fill (ohci_t *ohci, unsigned int info,
 		data = 0;
 
 	td->hwINFO = ohci_cpu_to_le32 (info);
-	td->hwCBP = ohci_cpu_to_le32 (data);
+	td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
 	if (data)
-		td->hwBE = ohci_cpu_to_le32 (data + len - 1);
+		td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
 	else
 		td->hwBE = 0;
-	td->hwNextTD = ohci_cpu_to_le32 (td_pt);
+	td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
 	td->hwPSW [0] = ohci_cpu_to_le16 (((__u32)data & 0x0FFF) | 0xE000);
 
 	/* append to queue */