Fix style issues primarily in 85xx and 83xx boards.

    - C++ comments
    - Trailing white space
    - Indentation not by TAB
    - Excessive amount of empty lines
    - Trailing empty lines

6 files changed, 79 insertions, 92 deletions

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 7e80ced393..dcb34457b1 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -161,4 +161,3 @@ int cpu_init_r (void)
 {
 	return 0;
 }
-
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index d9daa3e528..d5fa811edf 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -45,12 +45,12 @@ void
 pci_mpc83xx_init(volatile struct pci_controller *hose)
 {
 	volatile immap_t *	immr;
-	volatile clk8349_t *	clk;	
+	volatile clk8349_t *	clk;
 	volatile law8349_t *	pci_law;
 	volatile pot8349_t *	pci_pot;
 	volatile pcictrl8349_t *	pci_ctrl;
 	volatile pciconf8349_t *	pci_conf;
-	
+
 	u8 val8,tmp8,ret;
 	u16 reg16,tmp16;
 	u32 val32,tmp32;
@@ -69,7 +69,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 	udelay(2000);
 	clk->occr = 0xff000000;
 	udelay(2000);
-	
+
 	/*
 	 * Configure PCI Local Access Windows
 	 */
@@ -89,7 +89,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
 	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-//#if defined(CONFIG_PCI_2)	
+
 	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
 	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
@@ -98,8 +98,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
 	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-//#endif	
-	
+
 	/*
 	 * Configure PCI Inbound Translation Windows
 	 */
@@ -131,13 +130,13 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 	val8 = 0x34;
 	ret = i2c_write(0x26,0x7,1,&val8,1);
 #if defined(PCI_64BIT)
-	val8 = 0xf4;		// PMC2<->PCI1  64bit
+	val8 = 0xf4;	/* PMC2<->PCI1  64bit */
 #elif defined(PCI_ALL_PCI1)
-	val8 = 0xf3;		// PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1  32bit
+	val8 = 0xf3;	/* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1  32bit */
 #elif defined(PCI_ONE_PCI1)
-	val8 = 0xf9;		// PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2  32bit
+	val8 = 0xf9;	/* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2  32bit */
 #elif defined(PCI_TWO_PCI1)
-	val8 = 0xf5;		// PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit
+	val8 = 0xf5;	/* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
 #else
 	val8 = 0xf5;
 #endif
@@ -160,7 +159,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 	pci_ctrl[0].gcr = 1;
 #ifndef PCI_64BIT
 	pci_ctrl[1].gcr = 1;
-#endif	
+#endif
 	udelay(2000);
 
 	hose[0].first_busno = 0;
@@ -186,7 +185,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 #define PCI_CLASS_BRIDGE	0x06
 	reg16 = 0xff;
 	tmp32 = 0xffff;
-	pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);	
+	pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
 
 	pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
 	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
@@ -219,7 +218,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
 			   (CFG_IMMRBAR+0x8380),
 			   (CFG_IMMRBAR+0x8384));
 
-	pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);	
+	pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
 	pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
 	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 	pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
diff --git a/cpu/mpc83xx/resetvec.S b/cpu/mpc83xx/resetvec.S
index 7593e73213..3dfcd0dcd5 100644
--- a/cpu/mpc83xx/resetvec.S
+++ b/cpu/mpc83xx/resetvec.S
@@ -2,5 +2,5 @@
 #ifndef FIXME
 #if 0
 	b _start_e500
-#endif	
+#endif
 #endif
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 5bd112ce6e..63dcd664be 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -36,20 +36,16 @@
 
 #ifdef CONFIG_SPD_EEPROM
 
-
 #if defined(CONFIG_DDR_ECC)
 extern void dma_init(void);
 extern uint dma_check(void);
 extern int dma_xfer(void *dest, uint count, void *src);
 #endif
 
-
 #ifndef	CFG_READ_SPD
 #define CFG_READ_SPD	i2c_read
 #endif
 
-
-
 /*
  * Convert picoseconds into clock cycles (rounding up if needed).
  */
@@ -67,14 +63,12 @@ picos_to_clk(int picos)
 	return clks;
 }
 
-
 unsigned int
 banksize(unsigned char row_dens)
 {
 	return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
 }
 
-
 long int spd_sdram(int(read_spd)(uint addr))
 {
 	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
@@ -86,8 +80,8 @@ long int spd_sdram(int(read_spd)(uint addr))
 	unsigned int law_size;
 	unsigned char caslat;
 	unsigned int trfc, trfc_clk, trfc_low;
-	
-#warning Current spd_sdram does not fit its usage... adjust implementation or API...	
+
+#warning Current spd_sdram does not fit its usage... adjust implementation or API...
 
 	CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 
@@ -111,7 +105,7 @@ long int spd_sdram(int(read_spd)(uint addr))
 	debug("\n");
 	debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
 	debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
-	
+
 	if (spd.nrows == 2) {
 		ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
 				  | ((banksize(spd.row_dens) >> 23) - 1) );
@@ -298,9 +292,12 @@ long int spd_sdram(int(read_spd)(uint addr))
 
 	udelay(500);
 
-
-	ddr->sdram_clk_cntl = 0x82000000;/*SS_EN=1, CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after address/command*/
-
+	/*
+	 * SS_EN=1,
+	 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
+	 * clock cycle after address/command
+	 */
+	ddr->sdram_clk_cntl = 0x82000000;
 
 	/*
 	 * Figure out the settings for the sdram_cfg register.  Build up
@@ -339,7 +336,6 @@ long int spd_sdram(int(read_spd)(uint addr))
 #endif
 
 	ddr->sdram_cfg = tmp;
-
 	asm("sync;isync");
 	udelay(500);
 
@@ -347,7 +343,6 @@ long int spd_sdram(int(read_spd)(uint addr))
 
 	return memsize;/*in MBytes*/
 }
-
 #endif /* CONFIG_SPD_EEPROM */
 
 
@@ -407,7 +402,7 @@ ddr_enable_ecc(unsigned int dram_size)
 	 */
 	ddr->err_disable = 0x00000000;
 	asm("sync;isync");
-#endif	
+#endif
 }
 
 #endif	/* CONFIG_DDR_ECC */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 6530fbfd3f..260137da82 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -101,7 +101,7 @@ int get_clocks (void)
 	u32 corecnf_tab_index;
 	u8  corepll;
 	u32 lcrr;
-	
+
 	u32 csb_clk;
 	u32 tsec1_clk;
 	u32 tsec2_clk;
@@ -113,10 +113,10 @@ int get_clocks (void)
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 ddr_clk;
-	
+
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
-		
+
 #ifndef CFG_HRCW_HIGH
 # error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
 #endif /* CFG_HCWD_HIGH */
@@ -133,7 +133,6 @@ int get_clocks (void)
 		/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
 		/* FIXME: findout if there is a way to issue some warning */
 		return -2;
-		
 	}
 	if (im->clk.spmr & SPMR_CKID) {
 		pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
@@ -157,17 +156,16 @@ int get_clocks (void)
 #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
 
 	/* we have up to date pci_sync_in */
-	
 	spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
 	clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
-	
+
 	if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
 		csb_clk	= (pci_sync_in * spmf * (1 + clkin_div)) / 2;
 	}
 	else {
 		csb_clk = pci_sync_in * spmf * (1 + clkin_div);
 	}
-	
+
 	sccr = im->clk.sccr;
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
@@ -186,7 +184,7 @@ int get_clocks (void)
 		/* unkown SCCR_TSEC1CM value */
 		return -4;
 	}
-	
+
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -205,7 +203,7 @@ int get_clocks (void)
 		return -5;
 	}
 	i2c_clk = tsec2_clk;
-	
+
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
 		enc_clk = 0;
@@ -223,7 +221,7 @@ int get_clocks (void)
 		/* unkown SCCR_ENCCM value */
 		return -6;
 	}
-	
+
 	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 	case 0:
 		usbmph_clk = 0;
@@ -259,14 +257,14 @@ int get_clocks (void)
 		/* unkown SCCR_USBDRCM value */
 		return -8;
 	}
-	
+
 	if (usbmph_clk != 0
 		&& usbdr_clk != 0
 		&& usbmph_clk != usbdr_clk ) {
 		/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
 		return -9;
 	}
-	
+
 	lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
 	lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
@@ -279,9 +277,9 @@ int get_clocks (void)
 		/* unknown lcrr */
 		return -10;
 	}
-	
+
 	ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
-	
+
 	corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 	if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
@@ -310,7 +308,7 @@ int get_clocks (void)
 		/* unkown core to csb ratio */
 		return -12;
 	}
-	
+
 	gd->csb_clk    = csb_clk   ;
 	gd->tsec1_clk  = tsec1_clk ;
 	gd->tsec2_clk  = tsec2_clk ;
@@ -318,11 +316,11 @@ int get_clocks (void)
 	gd->usbmph_clk = usbmph_clk;
 	gd->usbdr_clk  = usbdr_clk ;
 	gd->i2c_clk    = i2c_clk   ;
-	gd->enc_clk    = enc_clk   ;	
+	gd->enc_clk    = enc_clk   ;
 	gd->lbiu_clk   = lbiu_clk  ;
 	gd->lclk_clk   = lclk_clk  ;
 	gd->ddr_clk    = ddr_clk   ;
-	
+
 	gd->cpu_clk = gd->core_clk;
 	gd->bus_clk = gd->lbiu_clk;
 	return 0;
@@ -341,7 +339,7 @@ ulong get_bus_freq (ulong dummy)
 int print_clock_conf (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	
+
 	printf("Clock configuration:\n");
 	printf("  Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
 	printf("  Core:                %4d MHz\n",gd->core_clk/1000000);
@@ -353,7 +351,7 @@ int print_clock_conf (void)
 	printf("  TSEC2:               %4d MHz\n",gd->tsec2_clk/1000000);
 	printf("  USB MPH:             %4d MHz\n",gd->usbmph_clk/1000000);
 	printf("  USB DR:              %4d MHz\n",gd->usbdr_clk/1000000);
-	
+
 #if 0
 	DECLARE_GLOBAL_DATA_PTR;
 
@@ -419,6 +417,5 @@ int print_clock_conf (void)
 	}
 	putc ('\n');
 #endif
-	return (0);
+	return 0;
 }
-
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index e9f07901b8..fb001a654c 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -28,7 +28,7 @@
  */
 
 #include <config.h>
-#include <mpc83xx.h> 
+#include <mpc83xx.h>
 #include <version.h>
 
 #define CONFIG_83XX	1		/* needed for Linux kernel header files*/
@@ -89,7 +89,7 @@ version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
 	.ascii " ", CONFIG_IDENT_STRING, "\0"
-	
+
 	.text
 #define _HRCW_TABLE_ENTRY(w)		\
 	.fill	8,1,(((w)>>24)&0xff);	\
@@ -101,7 +101,6 @@ version_string:
 	_HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
 
 
-	
 #ifndef CONFIG_DEFAULT_IMMR
 #error CONFIG_DEFAULT_IMMR must be defined
 #endif /* CFG_DEFAULT_IMMR */
@@ -143,7 +142,7 @@ _start: /* time t 0 */
 	. = EXC_OFF_SYS_RESET + 0x10
 
 	.globl	_start_warm
-_start_warm: 
+_start_warm:
 	li	r21, BOOTFLAG_WARM	/* Software reboot	*/
 	b	boot_warm
 
@@ -156,12 +155,12 @@ boot_warm: /* time t 5 */
 	lis	r3, CFG_IMMRBAR@h
 	ori	r3, r3, CFG_IMMRBAR@l
 	stw	r3, IMMRBAR(r4)
-	
+
 	/* Initialise the E300 processor core		*/
 	/*------------------------------------------*/
-	
+
 	bl	init_e300_core
-	
+
 #ifndef CFG_RAMBOOT
 
 	/* Inflate flash location so it appears everywhere, calculate */
@@ -218,7 +217,7 @@ _start_of_vectors:
 /* External Interrupt exception. */
 #ifndef FIXME
 	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
-#endif	
+#endif
 
 /* Alignment exception. */
 	. = 0x600
@@ -417,9 +416,9 @@ init_e300_core: /* time t 10 */
 	lis r4, CFG_WATCHDOG_VALUE
 	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
 	stw r4, SWCRR(r3)
-	
+
 	/* and reset it */
-	
+
 	li	r4, 0x556C
 	sth	r4, SWSRR@l(r3)
 	li	r4, 0xAA39
@@ -502,7 +501,7 @@ init_e300_core: /* time t 10 */
 
 	/* Done!						*/
 	/*------------------------------*/
-	blr 
+	blr
 
 /* Cache functions.
  *
@@ -645,8 +644,8 @@ relocate_code:
 	mtctr	r0
 	la	r8,-4(r4)
 	la	r7,-4(r3)
-	
-	/* and compare */	
+
+	/* and compare */
 20:	lwzu	r20,4(r8)
 	lwzu	r21,4(r7)
 	xor. r22, r20, r21
@@ -664,21 +663,19 @@ relocate_code:
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
-	
-	
 
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
-4:	
+4:
 	bl un_setup_stack_in_data_cache
 	mr r7, r3
 	mr r8, r4
 	bl dcache_disable
 	mr r3, r7
 	mr r4, r8
-	
+
 	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f	/* Always flush prefetch queue in any case */
@@ -889,9 +886,9 @@ map_flash_by_law1:
 	/* Address Mask in OR0 so ROM appears everywhere      */
 	/*----------------------------------------------------*/
 	lis	r3, (CFG_IMMRBAR)@h  /* r3 <= CFG_IMMRBAR    */
-	lwz	r4, OR0@l(r3)     
+	lwz	r4, OR0@l(r3)
 	li	r5, 0x7fff        /* r5 <= 0x00007FFFF */
-	and	r4, r4, r5        
+	and	r4, r4, r5
 	stw	r4, OR0@l(r3)     /* OR0 <= OR0 & 0x00007FFFF */
 
 	/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
@@ -926,9 +923,9 @@ remap_flash_by_law0:
 	/* Initialize the BR0 with the boot ROM starting address. */
 	lwz r4, BR0(r3)
 	li  r5, 0x7FFF
-	and r4, r4, r5             
+	and r4, r4, r5
 	lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
-	ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l 
+	ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
 	or  r5, r5, r4
 	stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
 
@@ -950,9 +947,9 @@ remap_flash_by_law0:
 	stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
 	blr
 
-setup_stack_in_data_cache_on_r1: 
+setup_stack_in_data_cache_on_r1:
 	lis r3, (CFG_IMMRBAR)@h
-	
+
 	/* setup D-BAT for the D-Cache (with out real memory backup) */
 
 	lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
@@ -961,13 +958,13 @@ setup_stack_in_data_cache_on_r1:
 	mtspr	DBAT0L, r4
 	isync
 
-#if 0	
+#if 0
 	/* Enable MMU */
 	mfmsr r4
 	ori r4, r4, (MSR_DR | MSR_IR)@l
 	mtmsr r4
-#endif	
-	
+#endif
+
 	/* Enable and invalidate data cache. */
 	mfspr	r4, HID0
 	mr	r5, r4
@@ -977,19 +974,19 @@ setup_stack_in_data_cache_on_r1:
 	mtspr	HID0, r4
 	mtspr	HID0, r5
 	sync
-	
+
 	/* Allocate Initial RAM in data cache.*/
 	li  r0, 0
 	lis	r4, (CFG_INIT_RAM_ADDR)@h
 	ori	r4, r4, (CFG_INIT_RAM_ADDR)@l
-	li	r5, 128*8 /* 128*8*32=32Kb */ 
+	li	r5, 128*8 /* 128*8*32=32Kb */
 	mtctr	r5
 1:
 	dcbz	r0, r4
 	addi	r4, r4, 32
 	bdnz	1b
 	isync
-		
+
 	/* Lock all the D-cache, basically leaving the reset of the program without dcache */
 	mfspr	r4, HID0
 	ori	r4, r4, (HID0_DLOCK)@l
@@ -1010,14 +1007,14 @@ un_setup_stack_in_data_cache:
 	blr
 	mr r14, r4
 	mr r15, r5
-	
+
 
 	lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
 	mtspr	DBAT0U, r4
 	ori r4, r4, 0x0002
 	mtspr	DBAT0L, r4
 	isync
-	
+
 	/* un lock all the D-cache */
 	mfspr	r4, HID0
 	lis r5, (~(HID0_DLOCK))@h
@@ -1030,20 +1027,20 @@ un_setup_stack_in_data_cache:
 	li  r0, 0
 	lis	r4, (CFG_INIT_RAM_ADDR)@h
 	ori	r4, r4, (CFG_INIT_RAM_ADDR)@l
-	li	r5, 128*8 /* 128*8*32=32Kb */ 
+	li	r5, 128*8 /* 128*8*32=32Kb */
 	mtctr	r5
 1:
 	dcbz	r0, r4
 	addi	r4, r4, 32
 	bdnz	1b
 	isync
-	
+
 	mflr r16
 	bl dcache_disable
 	mtlr r16
-	
+
 	blr
-	
+
 #if 0
 #define GREEN_LIGHT 0x2B0D4046
 #define RED_LIGHT   0x250D4046
@@ -1054,7 +1051,7 @@ un_setup_stack_in_data_cache:
  */
 
 	.globl liblight
-liblight:	
+liblight:
 	lis	r3, CFG_IMMRBAR@h
 	ori	r3, r3, CFG_IMMRBAR@l
 	li r4, 0x3002
@@ -1063,7 +1060,7 @@ liblight:
 	mtspr	HID0, r4
 	mtspr	HID2, r4
 	lis r4, 0xF8000000@h
-	ori r4, r4, 0xF8000000@l	
+	ori r4, r4, 0xF8000000@l
 	stw r4, LBLAWBAR1(r3)
 	lis r4, 0x8000000E@h
 	ori r4, r4, 0x8000000E@l
@@ -1083,14 +1080,14 @@ liblight:
 	ori r6, r6, RED_LIGHT@l
 	lis r7, LIB_CNT@h
 	ori r7, r7, LIB_CNT@l
-	
+
 1:
 	stw r5, 0(r4)
-	mtctr r7	
+	mtctr r7
 2:	bdnz 2b
 	stw r6, 0(r4)
-	mtctr r7	
+	mtctr r7
 3:	bdnz 3b
 	b 1b
-	
+
 #endif