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| author | Wolfgang Denk <wd@denx.de> | 2008-02-15 00:06:18 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-02-15 00:06:18 +0100 |
| commit | 6f99eec3dc2285abfb93631003f7e5cadf2eab0f (patch) | |
| tree | 1eaaa31eb768d8bfa68e9ff41eef53d37b64f21c /cpu/bf533/cpu.c | |
| parent | f6921e3dc331293c873ec4d109fd5517a42a90b3 (diff) | |
| parent | 30942b18b66f35f2ceedab39af10e9eccaa943cc (diff) | |
| download | u-boot-midas-6f99eec3dc2285abfb93631003f7e5cadf2eab0f.tar.gz u-boot-midas-6f99eec3dc2285abfb93631003f7e5cadf2eab0f.tar.bz2 u-boot-midas-6f99eec3dc2285abfb93631003f7e5cadf2eab0f.zip | |
Merge branch 'master' of git://www.denx.de/git/u-boot-blackfin
Conflicts:
Makefile
doc/README.standalone
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/bf533/cpu.c')
| -rw-r--r-- | cpu/bf533/cpu.c | 26 |
1 files changed, 9 insertions, 17 deletions
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c index 8118861f8d..edb771e33c 100644 --- a/cpu/bf533/cpu.c +++ b/cpu/bf533/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -190,13 +184,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application |