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| author | Stefan Roese <sr@denx.de> | 2007-06-06 11:42:13 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-06 11:42:13 +0200 |
| commit | c440bfe6d6d92d66478a7e84402b31f48413617b (patch) | |
| tree | 7919ffbc5fdf5a1bb7dddf066ae904aad1058135 /board/amcc/acadia/acadia.c | |
| parent | e3cbe1f93c5722f8ebbad468e30c069a2b511097 (diff) | |
| download | u-boot-midas-c440bfe6d6d92d66478a7e84402b31f48413617b.tar.gz u-boot-midas-c440bfe6d6d92d66478a7e84402b31f48413617b.tar.bz2 u-boot-midas-c440bfe6d6d92d66478a7e84402b31f48413617b.zip | |
ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/acadia/acadia.c')
| -rw-r--r-- | board/amcc/acadia/acadia.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 3b63c8a741..46d63e6308 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -63,8 +63,14 @@ int board_early_init_f(void) acadia_gpio_init(); /* Configure 405EZ for NAND usage */ - mtsdr(sdrnand0, 0x80c00000); - mtsdr(sdrultra0, 0x8d110000); + mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); + mfsdr(sdrultra0, reg); + reg &= ~SDR_ULTRA0_CSN_MASK; + reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) | + SDR_ULTRA0_NDGPIOBP | + SDR_ULTRA0_EBCRDYEN | + SDR_ULTRA0_NFSRSTEN; + mtsdr(sdrultra0, reg); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); |