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| author | Stefan Roese <sr@denx.de> | 2015-07-16 10:40:05 +0200 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-08-17 18:49:02 +0200 |
| commit | 2a0b7dc3b6ce4e4994ef71dcd6fbb31000c2ae47 (patch) | |
| tree | 26ae347416c6cd0980a57ee7ffadcf4322ad0ce4 /board/Marvell | |
| parent | 501c098a1f2cdaa930cb1a7166d3724467890a64 (diff) | |
| download | u-boot-midas-2a0b7dc3b6ce4e4994ef71dcd6fbb31000c2ae47.tar.gz u-boot-midas-2a0b7dc3b6ce4e4994ef71dcd6fbb31000c2ae47.tar.bz2 u-boot-midas-2a0b7dc3b6ce4e4994ef71dcd6fbb31000c2ae47.zip | |
arm: mvebu: Enable NAND controller on MVEBU SoC's
This patch enables the NAND controller on the Armada XP/38x and provides
a new function that returns the NAND controller input clock. This
function will be used by the MVEBU NAND driver.
As part of this patch, the multiple BIT macro definitions are moved
to a common place in soc.h.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Peter Morrow <peter@senient.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Diffstat (limited to 'board/Marvell')
| -rw-r--r-- | board/Marvell/db-88f6820-gp/db-88f6820-gp.c | 2 | ||||
| -rw-r--r-- | board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e661fa1296..0eb17f62a2 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -15,8 +15,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BIT(nr) (1UL << (nr)) - #define ETH_PHY_CTRL_REG 0 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c index 00ca878873..78c7b7e4e6 100644 --- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c +++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c @@ -12,8 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define BIT(nr) (1UL << (nr)) - #define ETH_PHY_CTRL_REG 0 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) |