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| author | Stefan Roese <sr@denx.de> | 2010-07-20 07:06:03 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-07-23 09:54:09 +0200 |
| commit | eab9800182a0ff5ee2a9d7055a91dd9360ed681f (patch) | |
| tree | 077958172146cbe7f21607f9cf3805f98169329b /arch | |
| parent | 5bf39a96c2b236baf8ef5b7a1e78a18f83152f27 (diff) | |
| download | u-boot-midas-eab9800182a0ff5ee2a9d7055a91dd9360ed681f.tar.gz u-boot-midas-eab9800182a0ff5ee2a9d7055a91dd9360ed681f.tar.bz2 u-boot-midas-eab9800182a0ff5ee2a9d7055a91dd9360ed681f.zip | |
ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values
Using this define, a board can define an opimized RFDC value and use
the auto calibration code to "tune" the remaining DDR2 controller
calibration register.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 0f69ef97ee..2fee995690 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -767,6 +767,13 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) debug("\n\n"); +#if defined(CONFIG_DDR_RFDC_FIXED) + mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED); + size = 512; + rffd_average = CONFIG_DDR_RFDC_FIXED & SDRAM_RFDC_RFFD_MASK; + mfsdram(SDRAM_RDCC, rdcc); /* record this value */ + cal->rdcc = rdcc; +#else /* CONFIG_DDR_RFDC_FIXED */ in_window = 0; rdcc = 0; @@ -830,6 +837,7 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal) rffd_average = SDRAM_RFDC_RFFD_MAX; mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); +#endif /* CONFIG_DDR_RFDC_FIXED */ rffd = rffd_average; in_window = 0; @@ -1211,10 +1219,14 @@ u32 DQS_autocalibration(void) debug("*** best_result: read value SDRAM_RQDC 0x%08x\n", rqdc_reg); +#if defined(CONFIG_DDR_RFDC_FIXED) + mtsdram(SDRAM_RFDC, CONFIG_DDR_RFDC_FIXED); +#else /* CONFIG_DDR_RFDC_FIXED */ mfsdram(SDRAM_RFDC, rfdc_reg); rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(tcal.autocal.rffd)); +#endif /* CONFIG_DDR_RFDC_FIXED */ mfsdram(SDRAM_RFDC, rfdc_reg); debug("*** best_result: read value SDRAM_RFDC 0x%08x\n", |