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authorSimon Glass <sjg@chromium.org>2015-01-27 22:13:47 -0700
committerSimon Glass <sjg@chromium.org>2015-02-06 12:07:39 -0700
commit3a1a18ff1867d6f94921a24992354d3a547666d6 (patch)
treec3501a0edb1d3e92cf863c8f7b31bd32b0586878 /arch/x86/cpu/baytrail/valleyview.c
parent00bdd95278e189131f9b5858045c540bf0cce530 (diff)
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x86: Add support for Intel Minnowboard Max
This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/baytrail/valleyview.c')
-rw-r--r--arch/x86/cpu/baytrail/valleyview.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
new file mode 100644
index 0000000000..a3e837d43e
--- /dev/null
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <pci_ids.h>
+#include <asm/post.h>
+
+static struct pci_device_id mmc_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
+};
+
+int cpu_mmc_init(bd_t *bis)
+{
+ printf("mmc init\n");
+ return pci_mmc_init("ValleyView SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
+}
+
+int arch_cpu_init(void)
+{
+ int ret;
+
+ post_code(POST_CPU_INIT);
+#ifdef CONFIG_SYS_X86_TSC_TIMER
+ timer_set_base(rdtsc());
+#endif
+
+ ret = x86_cpu_init_f();
+ if (ret)
+ return ret;
+
+ return 0;
+}