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authorLokesh Vutla <lokeshvutla@ti.com>2015-07-28 14:16:45 +0530
committerTom Rini <trini@konsulko.com>2015-08-12 20:47:53 -0400
commit74af583e9f7a255443d8f625c8dce6da7b9703be (patch)
treefbd63bb5fad0a796a8dcfcf4cfca0623fa235f17 /arch/arm/mach-keystone/include/mach/clock-k2hk.h
parent7b50e1599f4e6551a3348ca5f061a596f6f6896e (diff)
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ARM: keystone2: Use common structure for PLLs
Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach/clock-k2hk.h')
-rw-r--r--arch/arm/mach-keystone/include/mach/clock-k2hk.h9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index c41210c134..366bf0ee59 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];
#define KS2_CLK1_6 sys_clk0_6_clk
-/* PLL identifiers */
-enum pll_type_e {
- CORE_PLL,
- PASS_PLL,
- TETRIS_PLL,
- DDR3A_PLL,
- DDR3B_PLL,
-};
-
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}