diff options
| author | James Doublesin <doublesin@ti.com> | 2014-12-22 16:26:11 -0600 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-13 11:53:39 -0500 |
| commit | fc46bae2ae38c8d0b1570427b5c9520281eaae4f (patch) | |
| tree | c2536bc12569eb79405935eaabb2737dfc4e8aac /arch/arm/include/asm/arch-am33xx | |
| parent | e2a6207bcc45d9d8f3c2da75d581f3efb4d7e47f (diff) | |
| download | u-boot-midas-fc46bae2ae38c8d0b1570427b5c9520281eaae4f.tar.gz u-boot-midas-fc46bae2ae38c8d0b1570427b5c9520281eaae4f.tar.bz2 u-boot-midas-fc46bae2ae38c8d0b1570427b5c9520281eaae4f.zip | |
arm: am437x: Enable hardware leveling for EMIF
Switch to using hardware leveling for certain parameters on the EMIF
rather than using precalculated values. Doing this also means we have a
common place now between am437x and am335x for setting
emif_sdram_ref_ctrl with a value for the correct delay length.
Tested-by: Felipe Balbi <balbi@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 11 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware_am33xx.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 1 |
3 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 8dd69b3c80..b94b56cba7 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -219,6 +219,12 @@ struct cm_dpll { unsigned int resv4[2]; unsigned int clklcdcpixelclk; /* offset 0x34 */ }; + +struct prm_device_inst { + unsigned int prm_rstctrl; + unsigned int prm_rsttime; + unsigned int prm_rstst; +}; #else /* Encapsulating core pll registers */ struct cm_wkuppll { @@ -386,6 +392,11 @@ struct cm_device_inst { unsigned int cm_dll_ctrl; }; +struct prm_device_inst { + unsigned int prm_rstctrl; + unsigned int prm_rstst; +}; + struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index c67a0801a9..d1aed58503 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -39,6 +39,7 @@ /* VTP Base address */ #define VTP0_CTRL_ADDR 0x44E10E0C #define VTP1_CTRL_ADDR 0x48140E10 +#define PRM_DEVICE_INST 0x44E00F00 /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index efdecf4613..29e3816c1a 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -71,6 +71,7 @@ #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) #define CM_DEVICE_INST 0x44df4100 +#define PRM_DEVICE_INST 0x44df4000 /* Control status register */ #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) |