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| author | Marek Vasut <marek.vasut@gmail.com> | 2010-09-09 09:50:39 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-10-19 22:46:22 +0200 |
| commit | 3ba8bf7c6d6c09b9823b08b03d2d155907313238 (patch) | |
| tree | dcb9243cd47eb640e306ba6eba658e14b7429809 /arch/arm/cpu/pxa/usb.c | |
| parent | 9f80a20e05f20ab6b20be3addee969e1306ee3d5 (diff) | |
| download | u-boot-midas-3ba8bf7c6d6c09b9823b08b03d2d155907313238.tar.gz u-boot-midas-3ba8bf7c6d6c09b9823b08b03d2d155907313238.tar.bz2 u-boot-midas-3ba8bf7c6d6c09b9823b08b03d2d155907313238.zip | |
PXA: pxa-regs.h cleanup
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Diffstat (limited to 'arch/arm/cpu/pxa/usb.c')
| -rw-r--r-- | arch/arm/cpu/pxa/usb.c | 61 |
1 files changed, 27 insertions, 34 deletions
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index bd718a6fff..0311d5e997 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -27,86 +27,79 @@ # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) #include <asm/arch/pxa-regs.h> +#include <asm/io.h> #include <usb.h> int usb_cpu_init(void) { #if defined(CONFIG_CPU_MONAHANS) /* Enable USB host clock. */ - CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC); + writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); udelay(100); #endif #if defined(CONFIG_PXA27X) /* Enable USB host clock. */ - CKEN |= CKEN10_USBHOST; + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); #endif #if defined(CONFIG_CPU_MONAHANS) /* Configure Port 2 for Host (USB Client Registers) */ - UP2OCR = 0x3000c; + writel(0x3000c, UP2OCR); #endif - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); wait_ms(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCHR |= UHCHR_FSBIR; - while (UHCHR & UHCHR_FSBIR) + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + while (readl(UHCHR) & UHCHR_FSBIR) udelay(1); #if defined(CONFIG_CPU_MONAHANS) - UHCHR &= ~UHCHR_SSEP0; + writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_PXA27X) - UHCHR &= ~UHCHR_SSEP2; + writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); #endif - UHCHR &= ~UHCHR_SSEP1; - UHCHR &= ~UHCHR_SSE; + writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); return 0; } int usb_cpu_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS); udelay(10); #if defined(CONFIG_CPU_MONAHANS) - UHCHR |= UHCHR_SSEP0; + writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_PXA27X) - UHCHR |= UHCHR_SSEP2; + writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); #endif - UHCHR |= UHCHR_SSEP1; - UHCHR |= UHCHR_SSE; - - return 0; -} - -int usb_cpu_init_fail(void) -{ - UHCHR |= UHCHR_FHR; - udelay(11); - UHCHR &= ~UHCHR_FHR; - - UHCCOMS |= 1; - udelay(10); + writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); #if defined(CONFIG_CPU_MONAHANS) - UHCHR |= UHCHR_SSEP0; + /* Disable USB host clock. */ + writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); + udelay(100); #endif #if defined(CONFIG_PXA27X) - UHCHR |= UHCHR_SSEP2; + /* Disable USB host clock. */ + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); #endif - UHCHR |= UHCHR_SSEP1; - UHCHR |= UHCHR_SSE; return 0; } +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} + # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ |