1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
/* Check that the tst Rm,Rn instruction is generated for QImode and HImode
values loaded from memory. If everything goes as expected we won't see
any sign/zero extensions or and ops. On SH2A we don't expect to see the
movu insn. */
/* { dg-do compile } */
/* { dg-options "-O1" } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
/* { dg-final { scan-assembler-times "tst\tr" 8 } } */
/* { dg-final { scan-assembler-not "tst\t#255" } } */
/* { dg-final { scan-assembler-not "exts|extu|and|movu" } } */
int
test00 (char* a, char* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test01 (unsigned char* a, unsigned char* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test02 (short* a, short* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test03 (unsigned short* a, unsigned short* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test04 (char* a, short* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test05 (short* a, char* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test06 (int* a, char* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
int
test07 (int* a, short* b, int c, int d)
{
if (*a & *b)
return c;
return d;
}
|