1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
|
;; Pentium Scheduling
;; Copyright (C) 2002-2014 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;;
;; The Pentium is an in-order core with two integer pipelines.
;; True for insns that behave like prefixed insns on the Pentium.
(define_attr "pent_prefix" "false,true"
(if_then_else (ior (eq_attr "prefix_0f" "1")
(ior (eq_attr "prefix_data16" "1")
(eq_attr "prefix_rep" "1")))
(const_string "true")
(const_string "false")))
;; Categorize how an instruction slots.
;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
;; rules, because it results in noticeably better code on non-MMX Pentium
;; and doesn't hurt much on MMX. (Prefixed instructions are not very
;; common, so the scheduler usually has a non-prefixed insn to pair).
(define_attr "pent_pair" "uv,pu,pv,np"
(cond [(eq_attr "imm_disp" "true")
(const_string "np")
(ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
(and (eq_attr "type" "pop,push")
(eq_attr "memory" "!both")))
(if_then_else (eq_attr "pent_prefix" "true")
(const_string "pu")
(const_string "uv"))
(eq_attr "type" "ibr")
(const_string "pv")
(and (eq_attr "type" "ishift")
(match_operand 2 "const_int_operand"))
(const_string "pu")
(and (eq_attr "type" "rotate")
(match_operand 2 "const1_operand"))
(const_string "pu")
(and (eq_attr "type" "ishift1")
(match_operand 1 "const_int_operand"))
(const_string "pu")
(and (eq_attr "type" "rotate1")
(match_operand 1 "const1_operand"))
(const_string "pu")
(and (eq_attr "type" "call")
(match_operand 0 "constant_call_address_operand"))
(const_string "pv")
(and (eq_attr "type" "callv")
(match_operand 1 "constant_call_address_operand"))
(const_string "pv")
]
(const_string "np")))
(define_automaton "pentium,pentium_fpu")
;; Pentium do have U and V pipes. Instruction to both pipes
;; are always issued together, much like on VLIW.
;;
;; predecode
;; / \
;; decodeu decodev
;; / | |
;; fpu executeu executev
;; | | |
;; fpu retire retire
;; |
;; fpu
;; We add dummy "port" pipes allocated only first cycle of
;; instruction to specify this behavior.
(define_cpu_unit "pentium-portu,pentium-portv" "pentium")
(define_cpu_unit "pentium-u,pentium-v" "pentium")
(absence_set "pentium-portu" "pentium-u,pentium-v")
(presence_set "pentium-portv" "pentium-portu")
;; Floating point instructions can overlap with new issue of integer
;; instructions. We model only first cycle of FP pipeline, as it is
;; fully pipelined.
(define_cpu_unit "pentium-fp" "pentium_fpu")
;; There is non-pipelined multiplier unit used for complex operations.
(define_cpu_unit "pentium-fmul" "pentium_fpu")
;; Pentium preserves memory ordering, so when load-execute-store
;; instruction is executed together with other instruction loading
;; data, the execution of the other instruction is delayed to very
;; last cycle of first instruction, when data are bypassed.
;; We model this by allocating "memory" unit when store is pending
;; and using conflicting load units together.
(define_cpu_unit "pentium-memory" "pentium")
(define_cpu_unit "pentium-load0" "pentium")
(define_cpu_unit "pentium-load1" "pentium")
(absence_set "pentium-load0,pentium-load1" "pentium-memory")
(define_reservation "pentium-load" "(pentium-load0 | pentium-load1)")
(define_reservation "pentium-np" "(pentium-u + pentium-v)")
(define_reservation "pentium-uv" "(pentium-u | pentium-v)")
(define_reservation "pentium-portuv" "(pentium-portu | pentium-portv)")
(define_reservation "pentium-firstu" "(pentium-u + pentium-portu)")
(define_reservation "pentium-firstv" "(pentium-v + pentium-portuv)")
(define_reservation "pentium-firstuv" "(pentium-uv + pentium-portuv)")
(define_reservation "pentium-firstuload" "(pentium-load + pentium-firstu)")
(define_reservation "pentium-firstvload" "(pentium-load + pentium-firstv)")
(define_reservation "pentium-firstuvload" "(pentium-load + pentium-firstuv)
| (pentium-firstv,pentium-v,
(pentium-load+pentium-firstv))")
(define_reservation "pentium-firstuboth" "(pentium-load + pentium-firstu
+ pentium-memory)")
(define_reservation "pentium-firstvboth" "(pentium-load + pentium-firstv
+ pentium-memory)")
(define_reservation "pentium-firstuvboth" "(pentium-load + pentium-firstuv
+ pentium-memory)
| (pentium-firstv,pentium-v,
(pentium-load+pentium-firstv))")
;; Few common long latency instructions
(define_insn_reservation "pent_mul" 11
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "imul"))
"pentium-np*11")
(define_insn_reservation "pent_str" 12
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "str"))
"pentium-np*12")
;; Integer division and some other long latency instruction block all
;; units, including the FP pipe. There is no value in modeling the
;; latency of these instructions and not modeling the latency
;; decreases the size of the DFA.
(define_insn_reservation "pent_block" 1
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "idiv"))
"pentium-np+pentium-fp")
;; Moves usually have one cycle penalty, but there are exceptions.
(define_insn_reservation "pent_fmov" 1
(and (eq_attr "cpu" "pentium")
(and (eq_attr "type" "fmov")
(eq_attr "memory" "none,load")))
"(pentium-fp+pentium-np)")
(define_insn_reservation "pent_fpmovxf" 3
(and (eq_attr "cpu" "pentium")
(and (eq_attr "type" "fmov")
(and (eq_attr "memory" "load,store")
(eq_attr "mode" "XF"))))
"(pentium-fp+pentium-np)*3")
(define_insn_reservation "pent_fpstore" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "type" "fmov")
(ior (match_operand 1 "immediate_operand")
(eq_attr "memory" "store"))))
"(pentium-fp+pentium-np)*2")
(define_insn_reservation "pent_imov" 1
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "imov"))
"pentium-firstuv")
;; Push and pop instructions have 1 cycle latency and special
;; hardware bypass allows them to be paired with other push,pop
;; and call instructions.
(define_bypass 0 "pent_push,pent_pop" "pent_push,pent_pop,pent_call")
(define_insn_reservation "pent_push" 1
(and (eq_attr "cpu" "pentium")
(and (eq_attr "type" "push")
(eq_attr "memory" "store")))
"pentium-firstuv")
(define_insn_reservation "pent_pop" 1
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "pop,leave"))
"pentium-firstuv")
;; Call and branch instruction can execute in either pipe, but
;; they are only pairable when in the v pipe.
(define_insn_reservation "pent_call" 10
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "call,callv"))
"pentium-firstv,pentium-v*9")
(define_insn_reservation "pent_branch" 1
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "ibr"))
"pentium-firstv")
;; Floating point instruction dispatch in U pipe, but continue
;; in FP pipeline allowing other instructions to be executed.
(define_insn_reservation "pent_fp" 3
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "fop,fistp"))
"(pentium-firstu+pentium-fp),nothing,nothing")
;; First two cycles of fmul are not pipelined.
(define_insn_reservation "pent_fmul" 3
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "fmul"))
"(pentium-firstuv+pentium-fp+pentium-fmul),pentium-fmul,nothing")
;; Long latency FP instructions overlap with integer instructions,
;; but only last 2 cycles with FP ones.
(define_insn_reservation "pent_fdiv" 39
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "fdiv"))
"(pentium-np+pentium-fp+pentium-fmul),
(pentium-fp+pentium-fmul)*36,pentium-fmul*2")
(define_insn_reservation "pent_fpspc" 70
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "fpspc"))
"(pentium-np+pentium-fp+pentium-fmul),
(pentium-fp+pentium-fmul)*67,pentium-fmul*2")
;; Integer instructions. Load/execute/store takes 3 cycles,
;; load/execute 2 cycles and execute only one cycle.
(define_insn_reservation "pent_uv_both" 3
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "uv")
(eq_attr "memory" "both")))
"pentium-firstuvboth,pentium-uv+pentium-memory,pentium-uv")
(define_insn_reservation "pent_u_both" 3
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "pu")
(eq_attr "memory" "both")))
"pentium-firstuboth,pentium-u+pentium-memory,pentium-u")
(define_insn_reservation "pent_v_both" 3
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "pv")
(eq_attr "memory" "both")))
"pentium-firstvboth,pentium-v+pentium-memory,pentium-v")
(define_insn_reservation "pent_np_both" 3
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "np")
(eq_attr "memory" "both")))
"pentium-np,pentium-np,pentium-np")
(define_insn_reservation "pent_uv_load" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "uv")
(eq_attr "memory" "load")))
"pentium-firstuvload,pentium-uv")
(define_insn_reservation "pent_u_load" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "pu")
(eq_attr "memory" "load")))
"pentium-firstuload,pentium-u")
(define_insn_reservation "pent_v_load" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "pv")
(eq_attr "memory" "load")))
"pentium-firstvload,pentium-v")
(define_insn_reservation "pent_np_load" 2
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "np")
(eq_attr "memory" "load")))
"pentium-np,pentium-np")
(define_insn_reservation "pent_uv" 1
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "uv")
(eq_attr "memory" "none")))
"pentium-firstuv")
(define_insn_reservation "pent_u" 1
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "pu")
(eq_attr "memory" "none")))
"pentium-firstu")
(define_insn_reservation "pent_v" 1
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "pv")
(eq_attr "memory" "none")))
"pentium-firstv")
(define_insn_reservation "pent_np" 1
(and (eq_attr "cpu" "pentium")
(and (eq_attr "pent_pair" "np")
(eq_attr "memory" "none")))
"pentium-np")
|
