blob: ee0fbbda69ac84ae272b90950a8efdc32b957b3c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
|
;; Constraint definitions for SPARC.
;; Copyright (C) 2008 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;;; Unused letters:
;;; ABCD P Z
;;; a jkl q tuvwxyz
;; Register constraints
(define_register_constraint "b" "(TARGET_V9 && TARGET_VIS ? EXTRA_FP_REGS : NO_REGS)"
"Any floating-point register in VIS mode")
(define_register_constraint "c" "FPCC_REGS"
"Floating-point condition code register")
(define_register_constraint "d" "(TARGET_V9 && TARGET_VIS ? FP_REGS : NO_REGS)"
"Lower floating-point register in VIS mode")
;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
;; MD file for V8 and V9.
(define_register_constraint "e" "TARGET_V9 ? EXTRA_FP_REGS : FP_REGS"
"Any floating-point register")
(define_register_constraint "f" "FP_REGS"
"Lower floating-point register")
(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
"64-bit global or out register in V8+ mode")
;; Floating-point constant constraints
(define_constraint "G"
"The floating-point zero constant"
(and (match_code "const_double")
(match_test "const_zero_operand (op, mode)")))
;; Integer constant constraints
(define_constraint "H"
"Valid operand of double arithmetic operation"
(and (match_code "const_double")
(match_test "arith_double_operand (op, DImode)")))
(define_constraint "I"
"Signed 13-bit integer constant"
(and (match_code "const_int")
(match_test "SPARC_SIMM13_P (ival)")))
(define_constraint "J"
"The integer zero constant"
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "K"
"Signed 32-bit constant that can be loaded with a sethi instruction"
(and (match_code "const_int")
(match_test "SPARC_SETHI32_P (ival)")))
(define_constraint "L"
"Signed 11-bit integer constant"
(and (match_code "const_int")
(match_test "SPARC_SIMM11_P (ival)")))
(define_constraint "M"
"Signed 10-bit integer constant"
(and (match_code "const_int")
(match_test "SPARC_SIMM10_P (ival)")))
(define_constraint "N"
"Signed constant that can be loaded with a sethi instruction"
(and (match_code "const_int")
(match_test "SPARC_SETHI_P (ival)")))
(define_constraint "O"
"The 4096 constant"
(and (match_code "const_int")
(match_test "ival == 4096")))
;; Extra constraints
;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
;; i.e. accept pseudo-registers during reload.
(define_constraint "D"
"const_vector"
(and (match_code "const_vector")
(match_test "GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT")))
(define_constraint "Q"
"Floating-point constant that can be loaded with a sethi instruction"
(and (match_code "const_double")
(match_test "fp_sethi_p (op)")))
(define_constraint "R"
"Floating-point constant that can be loaded with a move instruction"
(and (match_code "const_double")
(match_test "fp_mov_p (op)")))
(define_constraint "S"
"Floating-point constant that can be loaded with a high/lo_sum sequence"
(and (match_code "const_double")
(match_test "fp_high_losum_p (op)")))
;; Not needed in 64-bit mode
(define_constraint "T"
"Memory reference whose address is aligned to 8-byte boundary"
(and (match_test "TARGET_ARCH32")
(match_code "mem,reg")
(match_test "memory_ok_for_ldd (op)")))
;; Not needed in 64-bit mode
(define_constraint "U"
"Pseudo-register or hard even-numbered integer register"
(and (match_test "TARGET_ARCH32")
(match_code "reg")
(ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
(not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
(match_test "register_ok_for_ldd (op)")))
;; Equivalent to 'T' but available in 64-bit mode
(define_constraint "W"
"Memory reference for 'e' constraint floating-point register"
(and (match_code "mem,reg")
(match_test "memory_ok_for_ldd (op)")))
(define_constraint "Y"
"The vector zero constant"
(and (match_code "const_vector")
(match_test "const_zero_operand (op, mode)")))
|
