blob: 7f551994b7d8daa7fa9ff95c843fc24116d343c8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
|
;; Constraint definitions for RS6000
;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Register constraints
(define_register_constraint "f" "TARGET_HARD_FLOAT && TARGET_FPRS
? FLOAT_REGS : NO_REGS"
"@internal")
(define_register_constraint "b" "BASE_REGS"
"@internal")
(define_register_constraint "h" "SPECIAL_REGS"
"@internal")
(define_register_constraint "q" "MQ_REGS"
"@internal")
(define_register_constraint "c" "CTR_REGS"
"@internal")
(define_register_constraint "l" "LINK_REGS"
"@internal")
(define_register_constraint "v" "ALTIVEC_REGS"
"@internal")
(define_register_constraint "x" "CR0_REGS"
"@internal")
(define_register_constraint "y" "CR_REGS"
"@internal")
(define_register_constraint "z" "XER_REGS"
"@internal")
;; Integer constraints
(define_constraint "I"
"A signed 16-bit constant"
(and (match_code "const_int")
(match_test "(unsigned HOST_WIDE_INT) (ival + 0x8000) < 0x10000")))
(define_constraint "J"
"high-order 16 bits nonzero"
(and (match_code "const_int")
(match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0")))
(define_constraint "K"
"low-order 16 bits nonzero"
(and (match_code "const_int")
(match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0")))
(define_constraint "L"
"signed 16-bit constant shifted left 16 bits"
(and (match_code "const_int")
(match_test "((ival & 0xffff) == 0
&& (ival >> 31 == -1 || ival >> 31 == 0))")))
(define_constraint "M"
"constant greater than 31"
(and (match_code "const_int")
(match_test "ival > 31")))
(define_constraint "N"
"positive constant that is an exact power of two"
(and (match_code "const_int")
(match_test "ival > 0 && exact_log2 (ival) >= 0")))
(define_constraint "O"
"constant zero"
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "P"
"constant whose negation is signed 16-bit constant"
(and (match_code "const_int")
(match_test "(unsigned HOST_WIDE_INT) ((- ival) + 0x8000) < 0x10000")))
;; Floating-point constraints
(define_constraint "G"
"Constant that can be copied into GPR with two insns for DF/DI
and one for SF."
(and (match_code "const_double")
(match_test "num_insns_constant (op, mode)
== (mode == SFmode ? 1 : 2)")))
(define_constraint "H"
"DF/DI constant that takes three insns."
(and (match_code "const_double")
(match_test "num_insns_constant (op, mode) == 3")))
;; Memory constraints
(define_memory_constraint "Q"
"Memory operand that is just an offset from a reg"
(and (match_code "mem")
(match_test "GET_CODE (XEXP (op, 0)) == REG")))
(define_memory_constraint "Y"
"Indexed or word-aligned displacement memory operand"
(match_operand 0 "word_offset_memref_operand"))
(define_memory_constraint "Z"
"Indexed or indirect memory operand"
(match_operand 0 "indexed_or_indirect_operand"))
;; Address constraints
(define_address_constraint "a"
"Indexed or indirect address operand"
(match_operand 0 "indexed_or_indirect_address"))
(define_constraint "R"
"AIX TOC entry"
(match_test "legitimate_constant_pool_address_p (op)"))
;; General constraints
(define_constraint "S"
"Constant that can be placed into a 64-bit mask operand"
(match_operand 0 "mask64_operand"))
(define_constraint "T"
"Constant that can be placed into a 32-bit mask operand"
(match_operand 0 "mask_operand"))
(define_constraint "U"
"V.4 small data reference"
(and (match_test "DEFAULT_ABI == ABI_V4")
(match_operand 0 "small_data_operand")))
(define_constraint "t"
"AND masks that can be performed by two rldic{l,r} insns
(but excluding those that could match other constraints of anddi3)"
(and (and (and (match_operand 0 "mask64_2_operand")
(match_test "(fixed_regs[CR0_REGNO]
|| !logical_operand (op, DImode))"))
(not (match_operand 0 "mask_operand")))
(not (match_operand 0 "mask64_operand"))))
(define_constraint "W"
"vector constant that does not require memory"
(match_operand 0 "easy_vector_constant"))
|
