1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
|
;; Predicate definitions for FR30.
;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Returns true if OP is an integer value suitable for use in an
;; ADDSP instruction.
(define_predicate "stack_add_operand"
(match_code "const_int")
{
return
(GET_CODE (op) == CONST_INT
&& INTVAL (op) >= -512
&& INTVAL (op) <= 508
&& ((INTVAL (op) & 3) == 0));
})
;; Returns true if OP is hard register in the range 8 - 15.
(define_predicate "high_register_operand"
(match_code "reg")
{
return
(GET_CODE (op) == REG
&& REGNO (op) <= 15
&& REGNO (op) >= 8);
})
;; Returns true if OP is hard register in the range 0 - 7.
(define_predicate "low_register_operand"
(match_code "reg")
{
return
(GET_CODE (op) == REG
&& REGNO (op) <= 7);
})
;; Returns true if OP is suitable for use in a CALL insn.
(define_predicate "call_operand"
(match_code "mem")
{
return (GET_CODE (op) == MEM
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == REG));
})
;; Returns TRUE if OP is a valid operand of a DImode operation.
(define_predicate "di_operand"
(match_code "const_int,const_double,reg,mem")
{
if (register_operand (op, mode))
return TRUE;
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
return FALSE;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
switch (GET_CODE (op))
{
case CONST_DOUBLE:
case CONST_INT:
return TRUE;
case MEM:
return memory_address_p (DImode, XEXP (op, 0));
default:
return FALSE;
}
})
;; Returns TRUE if OP is a DImode register or MEM.
(define_predicate "nonimmediate_di_operand"
(match_code "reg,mem")
{
if (register_operand (op, mode))
return TRUE;
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
return FALSE;
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
if (GET_CODE (op) == MEM)
return memory_address_p (DImode, XEXP (op, 0));
return FALSE;
})
;; Returns true if OP is an integer value suitable for use in an ADD
;; or ADD2 instruction, or if it is a register.
(define_predicate "add_immediate_operand"
(match_code "reg,const_int")
{
return
(GET_CODE (op) == REG
|| (GET_CODE (op) == CONST_INT
&& INTVAL (op) >= -16
&& INTVAL (op) <= 15));
})
|
