From 8c493ead6366b552adee796de296936b78f34c5a Mon Sep 17 00:00:00 2001 From: Ben Cheng Date: Sat, 17 May 2014 17:03:43 -0700 Subject: [4.9] Refresh GCC 4.9 to the 20140514 snapshot. For critical bug fixes including devirtualization and codegen. Change-Id: I8138d3dc408fc12db5eecb01d2753d39219712f2 --- gcc-4.9/gcc/ChangeLog | 717 +++++++++++++++++++-- gcc-4.9/gcc/DATESTAMP | 2 +- gcc-4.9/gcc/DEV-PHASE | 1 + gcc-4.9/gcc/asan.c | 15 + gcc-4.9/gcc/c-family/ChangeLog | 16 + gcc-4.9/gcc/c-family/c-common.c | 15 +- gcc-4.9/gcc/c-family/c-opts.c | 6 + gcc-4.9/gcc/c/ChangeLog | 12 + gcc-4.9/gcc/c/c-parser.c | 34 +- gcc-4.9/gcc/cfgexpand.c | 18 +- gcc-4.9/gcc/config.gcc | 1 - gcc-4.9/gcc/config/aarch64/aarch64.h | 12 +- gcc-4.9/gcc/config/alpha/alpha.c | 49 +- gcc-4.9/gcc/config/avr/avr-mcus.def | 2 +- gcc-4.9/gcc/config/avr/avr.c | 13 +- gcc-4.9/gcc/config/avr/avr.md | 8 +- gcc-4.9/gcc/config/i386/cygwin.h | 1 + gcc-4.9/gcc/config/i386/i386.c | 22 +- gcc-4.9/gcc/config/i386/i386.md | 11 +- gcc-4.9/gcc/config/i386/mingw32.h | 1 + gcc-4.9/gcc/config/msp430/msp430-protos.h | 3 +- gcc-4.9/gcc/config/msp430/msp430.c | 97 +-- gcc-4.9/gcc/config/msp430/msp430.md | 32 +- gcc-4.9/gcc/config/msp430/msp430.opt | 35 +- gcc-4.9/gcc/config/rs6000/altivec.md | 112 ++++ gcc-4.9/gcc/config/rs6000/dfp.md | 69 ++ gcc-4.9/gcc/config/rs6000/predicates.md | 9 +- gcc-4.9/gcc/config/rs6000/rs6000-builtin.def | 135 +++- gcc-4.9/gcc/config/rs6000/rs6000.c | 116 +++- gcc-4.9/gcc/config/rs6000/rs6000.h | 15 +- gcc-4.9/gcc/config/rs6000/rs6000.md | 255 +++++++- gcc-4.9/gcc/config/rs6000/sync.md | 105 ++- gcc-4.9/gcc/config/rs6000/vsx.md | 14 +- gcc-4.9/gcc/config/sh/sh.c | 8 +- gcc-4.9/gcc/config/sparc/sparc-protos.h | 1 - gcc-4.9/gcc/config/sparc/sparc.c | 16 - gcc-4.9/gcc/config/sparc/sparc.md | 304 +++++---- gcc-4.9/gcc/config/sparc/sparc.opt | 4 + gcc-4.9/gcc/config/sparc/sync.md | 19 +- gcc-4.9/gcc/configure | 2 +- gcc-4.9/gcc/configure.ac | 2 +- gcc-4.9/gcc/cp/ChangeLog | 51 ++ gcc-4.9/gcc/cp/call.c | 13 +- gcc-4.9/gcc/cp/init.c | 3 +- gcc-4.9/gcc/cp/lambda.c | 13 +- gcc-4.9/gcc/cp/parser.c | 38 +- gcc-4.9/gcc/cp/pt.c | 125 ++-- gcc-4.9/gcc/cp/typeck2.c | 2 +- gcc-4.9/gcc/doc/extend.texi | 67 +- gcc-4.9/gcc/doc/install.texi | 3 +- gcc-4.9/gcc/doc/invoke.texi | 34 +- gcc-4.9/gcc/doc/sourcebuild.texi | 31 +- gcc-4.9/gcc/fold-const.c | 4 - gcc-4.9/gcc/fortran/ChangeLog | 10 + gcc-4.9/gcc/fortran/resolve.c | 42 +- gcc-4.9/gcc/gimple-ssa-strength-reduction.c | 17 +- gcc-4.9/gcc/gimplify.c | 84 ++- gcc-4.9/gcc/go/gofrontend/import-archive.cc | 2 +- gcc-4.9/gcc/go/gofrontend/types.cc | 37 +- gcc-4.9/gcc/go/gofrontend/types.h | 10 +- gcc-4.9/gcc/graphite-scop-detection.c | 11 +- gcc-4.9/gcc/ipa-devirt.c | 11 + gcc-4.9/gcc/loop-init.c | 17 +- gcc-4.9/gcc/lto-streamer-out.c | 62 +- gcc-4.9/gcc/omp-low.c | 142 +++- gcc-4.9/gcc/opts.c | 10 +- gcc-4.9/gcc/passes.c | 34 +- gcc-4.9/gcc/po/ChangeLog | 4 + gcc-4.9/gcc/po/sv.po | 40 +- gcc-4.9/gcc/testsuite/ChangeLog | 337 +++++++++- .../gcc/testsuite/c-c++-common/gomp/atomic-16.c | 40 +- gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-11.C | 2 +- gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-27.C | 2 +- gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c | 2 +- gcc-4.9/gcc/testsuite/gcc.dg/vect/pr60505.c | 2 + .../gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c | 33 + gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx.c | 27 + gcc-4.9/gcc/testsuite/lib/target-supports.exp | 28 + gcc-4.9/gcc/tree-dfa.c | 2 +- gcc-4.9/gcc/tree-inline.c | 8 +- gcc-4.9/gcc/tree-nested.c | 22 + gcc-4.9/gcc/tree-ssa-loop-im.c | 24 +- gcc-4.9/gcc/tree-ssa-propagate.c | 12 +- gcc-4.9/gcc/tree-ssa-reassoc.c | 39 +- gcc-4.9/gcc/tree-ssa-structalias.c | 41 +- gcc-4.9/gcc/tree-ssa-threadedge.c | 88 ++- gcc-4.9/gcc/tree-tailcall.c | 16 +- gcc-4.9/gcc/tree-vect-data-refs.c | 8 +- gcc-4.9/gcc/tree-vect-generic.c | 3 +- gcc-4.9/gcc/tree-vect-loop.c | 13 +- gcc-4.9/gcc/tree-vect-slp.c | 42 +- gcc-4.9/gcc/tree-vectorizer.h | 5 +- gcc-4.9/gcc/tree.h | 3 + 93 files changed, 3281 insertions(+), 744 deletions(-) (limited to 'gcc-4.9/gcc') diff --git a/gcc-4.9/gcc/ChangeLog b/gcc-4.9/gcc/ChangeLog index c0f56a156..1ccda1cd6 100644 --- a/gcc-4.9/gcc/ChangeLog +++ b/gcc-4.9/gcc/ChangeLog @@ -1,3 +1,646 @@ +2014-05-14 Eric Botcazou + + * config/sparc/sparc-protos.h (sparc_absnegfloat_split_legitimate): + Delete. + * config/sparc/sparc.c (sparc_absnegfloat_split_legitimate): Likewise. + * config/sparc/sparc.md (fptype_ut699): New attribute. + (in_branch_delay): Return false if -mfix-ut699 is specified and + fptype_ut699 is set to single. + (truncdfsf2): Add fptype_ut699 attribute. + (fix_truncdfsi2): Likewise. + (floatsisf2): Change fptype attribute. + (fix_truncsfsi2): Likewise. + (negtf2_notv9): Delete. + (negtf2_v9): Likewise. + (negtf2_hq): New instruction. + (negtf2): New instruction and splitter. + (negdf2_notv9): Rewrite. + (abstf2_notv9): Delete. + (abstf2_hq_v9): Likewise. + (abstf2_v9): Likewise. + (abstf2_hq): New instruction. + (abstf2): New instruction and splitter. + (absdf2_notv9): Rewrite. + +2014-05-14 Matthias Klose + + Revert: + 2014-05-08 Manuel López-Ibáñez + Matthias Klose + + PR driver/61106 + * optc-gen.awk: Fix option handling for -Wunused-parameter. + +2014-05-13 Peter Bergner + + * doc/sourcebuild.texi: (dfp_hw): Document. + (p8vector_hw): Likewise. + (powerpc_eabi_ok): Likewise. + (powerpc_elfv2): Likewise. + (powerpc_htm_ok): Likewise. + (ppc_recip_hw): Likewise. + (vsx_hw): Likewise. + +2014-05-13 Jeff Law + + Backports fromm mainline: + + 2014-05-08 Jeff Law + + PR tree-optimization/61009 + * tree-ssa-threadedge.c (thread_through_normal_block): Return a + tri-state rather than a boolean. When a block is too big to + thread through, inform caller via negative return value. + (thread_across_edge): If a block was too big for normal threading, + then it's too big for a joiner too, so remove temporary equivalences + and return immediately. + + 2014-04-28 Jeff Law + + PR tree-optimization/60902 + * tree-ssa-threadedge.c + (record_temporary_equivalences_from_stmts_at_dest): Only iterate + over real defs when invalidating outputs from statements that do not + produce useful outputs for threading. + + 2014-04-23 Jeff Law + + PR tree-optimization/60902 + * tree-ssa-threadedge.c + (record_temporary_equivalences_from_stmts_at_dest): Make sure to + invalidate outputs from statements that do not produce useful + outputs for threading. + +2014-05-13 Richard Biener + + PR ipa/60973 + * tree-inline.c (remap_gimple_stmt): Clear tail call flag, + it needs revisiting whether the call still may be tail-called. + +2014-05-13 Jakub Jelinek + + PR target/61060 + * config/i386/i386.c (ix86_expand_set_or_movmem): If count_exp + is const0_rtx, return immediately. Don't test count == 0 when + it is always true. + +2014-05-12 Senthil Kumar Selvaraj + + Backport from mainline + 2014-05-12 Senthil Kumar Selvaraj + + PR target/60991 + * config/avr/avr.c (avr_out_store_psi): Use correct constant + to restore Y. + +2014-05-09 Uros Bizjak + + Backport from mainline + 2014-05-08 Uros Bizjak + + PR target/61092 + * config/alpha/alpha.c: Include gimple-iterator.h. + (alpha_gimple_fold_builtin): New function. Move + ALPHA_BUILTIN_UMULH folding from ... + (alpha_fold_builtin): ... here. + (TARGET_GIMPLE_FOLD_BUILTIN): New define. + +2014-05-09 Pitchumani Sivanupandi + + Backport from 2014-04-16 trunk r209446 + 2014-04-16 Pitchumani Sivanupandi + + * config/avr/avr-mcus.def: Correct typo for atxmega256a3bu macro. + +2014-05-09 Georg-Johann Lay + + Backport from 2014-05-09 trunk r210267 + + PR target/61055 + * config/avr/avr.md (cc): Add new attribute set_vzn. + (addqi3, addqq3, adduqq3, subqi3, subqq3, subuqq3, negqi2) [cc]: + Set cc insn attribute to set_vzn instead of set_zn for alternatives + with INC, DEC or NEG. + * config/avr/avr.c (avr_notice_update_cc): Handle SET_VZN. + (avr_out_plus_1): ADIW sets cc0 to CC_SET_CZN. + INC, DEC and ADD+ADC set cc0 to CC_CLOBBER. + +2014-05-08 Manuel López-Ibáñez + Matthias Klose + + PR driver/61106 + * optc-gen.awk: Fix option handling for -Wunused-parameter. + +2014-05-08 Uros Bizjak + + PR target/59952 + * config/i386/i386.c (PTA_HASWELL): Remove PTA_RTM. + +2014-05-05 Marek Polacek + + Back port from mainline + 2014-05-05 Marek Polacek + + PR driver/61065 + * opts.c (common_handle_option): Call error_at instead of warning_at. + +2014-05-04 Jan Hubicka + + PR ipa/60965 + * ipa-devirt.c (get_class_context): Allow POD to change to non-POD. + +2014-05-04 Peter Bergner + + * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define. + (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT. + (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT. + * config/rs6000/rs6000-builtin.def (BU_MISC_1): + Use RS6000_BTM_HARD_FLOAT. + (BU_MISC_2): Likewise. + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle + RS6000_BTM_HARD_FLOAT. + (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp + is explicitly used. + (rs6000_invalid_builtin): Add hard floating builtin support. + (rs6000_expand_builtin): Relax the gcc_assert to allow the new + hard float builtins. + (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT. + +2014-05-03 Joey Ye + + Backport from mainline r209463 + 2014-04-17 Joey Ye + + * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og. + +2014-05-03 Oleg Endo + + Back port from mainline + PR target/61026 + * config/sh/sh.c: Include stdlib headers before everything else. + +2014-05-02 Bill Schmidt + + PR tree-optimization/60930 + * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject + creating a multiply candidate by folding two constant + multiplicands when the result overflows. + +2014-05-02 Jakub Jelinek + + * gimplify.c (gimplify_adjust_omp_clauses_1): Handle + GOVD_FIRSTPRIVATE | GOVD_LASTPRIVATE. + (gimplify_adjust_omp_clauses): Simd region is never + directly nested in combined parallel. Instead, for linear + with copyin/copyout, if in combined for simd loop, make decl + firstprivate/lastprivate on OMP_FOR. + * omp-low.c (expand_omp_for_generic, expand_omp_for_static_nochunk, + expand_omp_for_static_chunk): When setting endvar, also set + fd->loop.v to the same value. + +2014-05-02 Kyrylo Tkachov + + Back port from mainline + 2014-04-24 Kyrylo Tkachov + + * config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Check + TARGET_SIMD rather than TARGET_GENERAL_REGS_ONLY. + (TARGET_SIMD): Take AARCH64_ISA_SIMD into account. + (TARGET_FLOAT): Take AARCH64_ISA_FP into account. + (TARGET_CRYPTO): Take TARGET_SIMD into account. + +2014-04-30 Michael Meissner + + Back port from mainline + 2014-04-24 Michael Meissner + + * doc/extend.texi (PowerPC Built-in Functions): Document new + powerpc extended divide, bcd, pack/unpack 128-bit, builtin + functions. + (PowerPC AltiVec/VSX Built-in Functions): Likewise. + + * config/rs6000/predicates.md (const_0_to_3_operand): New + predicate to match 0..3 integer constants. + + * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros + to support adding miscellaneous builtin functions. + (BU_DFP_MISC_2): Likewise. + (BU_P7_MISC_1): Likewise. + (BU_P7_MISC_2): Likewise. + (BU_P8V_MISC_3): Likewise. + (BU_MISC_1): Likewise. + (BU_MISC_2): Likewise. + (DIVWE): Add extended divide builtin functions. + (DIVWEO): Likewise. + (DIVWEU): Likewise. + (DIVWEUO): Likewise. + (DIVDE): Likewise. + (DIVDEO): Likewise. + (DIVDEU): Likewise. + (DIVDEUO): Likewise. + (DXEX): Add decimal floating-point builtin functions. + (DXEXQ): Likewise. + (DDEDPD): Likewise. + (DDEDPDQ): Likewise. + (DENBCD): Likewise. + (DENBCDQ): Likewise. + (DIEX): Likewise. + (DIEXQ): Likewise. + (DSCLI): Likewise. + (DSCLIQ): Likewise. + (DSCRI): Likewise. + (DSCRIQ): Likewise. + (CDTBCD): Add new BCD builtin functions. + (CBCDTD): Likewise. + (ADDG6S): Likewise. + (BCDADD): Likewise. + (BCDADD_LT): Likewise. + (BCDADD_EQ): Likewise. + (BCDADD_GT): Likewise. + (BCDADD_OV): Likewise. + (BCDSUB): Likewise. + (BCDSUB_LT): Likewise. + (BCDSUB_EQ): Likewise. + (BCDSUB_GT): Likewise. + (BCDSUB_OV): Likewise. + (PACK_TD): Add new pack/unpack 128-bit type builtin functions. + (UNPACK_TD): Likewise. + (PACK_TF): Likewise. + (UNPACK_TF): Likewise. + (UNPACK_TF_0): Likewise. + (UNPACK_TF_1): Likewise. + (PACK_V1TI): Likewise. + (UNPACK_V1TI): Likewise. + + * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add + support for decimal floating point builtin functions. + (rs6000_expand_ternop_builtin): Add checks for the new builtin + functions that take constant arguments. + (rs6000_invalid_builtin): Add decimal floating point builtin + support. + (rs6000_init_builtins): Setup long double, _Decimal64, and + _Decimal128 types for new builtin functions. + (builtin_function_type): Set the unsigned flags appropriately for + the new builtin functions. + (rs6000_opt_masks): Add support for decimal floating point builtin + functions. + + * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal + floating point builtin functions. + (RS6000_BTM_COMMON): Likewise. + (RS6000_BTI_long_double): Likewise. + (RS6000_BTI_dfloat64): Likewise. + (RS6000_BTI_dfloat128): Likewise. + (long_double_type_internal_node): Likewise. + (dfloat64_type_internal_node): Likewise. + (dfloat128_type_internal_node): Likewise. + + * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA + 2.07 bcd arithmetic instructions. + (UNSPEC_BCDSUB): Likewise. + (UNSPEC_BCD_OVERFLOW): Likewise. + (UNSPEC_BCD_ADD_SUB): Likewise. + (bcd_add_sub): Likewise. + (BCD_TEST): Likewise. + (bcd): Likewise. + (bcd_test): Likewise. + (bcd_test2): Likewise. + (bcd_): Likewise. + (peephole2 for combined bcd ops): Likewise. + + * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new + decimal floating point builtin functions. + (UNSPEC_DENBCD): Likewise. + (UNSPEC_DXEX): Likewise. + (UNSPEC_DIEX): Likewise. + (UNSPEC_DSCLI): Likewise. + (UNSPEC_DSCRI): Likewise. + (D64_D128): Likewise. + (dfp_suffix): Likewise. + (dfp_ddedpd_): Likewise. + (dfp_denbcd_): Likewise. + (dfp_dxex_): Likewise. + (dfp_diex_): Likewise. + (dfp_dscli_): Likewise. + (dfp_dscri_): Likewise. + + * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD + builtin functions. + (UNSPEC_CDTBCD): Likewise. + (UNSPEC_CBCDTD): Likewise. + (UNSPEC_DIVE): Add support for new extended divide builtin + functions. + (UNSPEC_DIVEO): Likewise. + (UNSPEC_DIVEU): Likewise. + (UNSPEC_DIVEUO): Likewise. + (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to + pack/unpack 128-bit types. + (UNSPEC_PACK_128BIT): Likewise. + (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. + (udiv3): Use idiv_ldiv mode attribute. + (div3): Likewise. + (addg6s): Add new BCD builtin functions. + (cdtbcd): Likewise. + (cbcdtd): Likewise. + (UNSPEC_DIV_EXTEND): Add support for new extended divide + instructions. + (div_extend): Likewise. + (div_"): Likewise. + (FP128_64): Add support for new builtin functions to pack/unpack + 128-bit types. + (unpack): Likewise. + (unpacktf_0): Likewise. + (unpacktf_1): Likewise. + (unpack_dm): Likewise. + (unpack_nodm): Likewise. + (pack): Likewise. + (unpackv1ti): Likewise. + (packv1ti): Likewise. + +2014-04-29 Pat Haugen + + Backport from mainline + 2014-04-17 Pat Haugen + + * config/rs6000/rs6000.md (addti3, subti3): New. + +2014-04-29 Jakub Jelinek + + PR tree-optimization/60971 + * tree-tailcall.c (process_assignment): Reject conversions which + reduce precision. + +2014-04-29 Nick Clifton + + * config/msp430/msp430.md (umulsidi): Fix typo. + (mulhisi3): Enable even inside interrupt handlers. + * config/msp430/msp430.c (msp430_print_operand): %O: Allow for the + bigger return address pushed in large mode. + +2014-04-28 Pat Haugen + + * config/rs6000/sync.md (AINT mode_iterator): Move definition. + (loadsync_): Change mode. + (load_quadpti, store_quadpti): New. + (atomic_load, atomic_store): Add support for TI mode. + * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. + +2014-04-28 Eric Botcazou + + * configure.ac: Tweak GAS check for LEON instructions on SPARC. + * configure: Regenerate. + * config/sparc/sparc.opt (muser-mode): New option. + * config/sparc/sync.md (atomic_compare_and_swap_1): Do not enable + for LEON3. + (atomic_compare_and_swap_leon3_1): New instruction for LEON3. + * doc/invoke.texi (SPARC options): Document -muser-mode. + +2014-04-26 Markus Trippelsdorf + + * doc/install.texi (Building with profile feedback): Remove + outdated sentence. + +2014-04-26 Tom de Vries + + * config/i386/i386.md (define_expand "ldexpxf3"): Fix out-of-bounds + array accesses. + +2014-04-25 Jakub Jelinek + + PR tree-optimization/60960 + * tree-vect-generic.c (expand_vector_operation): Only call + expand_vector_divmod if type's mode satisfies VECTOR_MODE_P. + +2014-04-25 Eric Botcazou + + PR target/60941 + * config/sparc/sparc.md (ashlsi3_extend): Delete. + +2014-04-25 Richard Biener + + PR ipa/60912 + * tree-ssa-structalias.c (ipa_pta_execute): Compute direct + call stmt use/clobber sets during stmt walk instead of + walking the possibly incomplete set of caller edges. + +2014-04-25 Richard Biener + + PR ipa/60911 + * passes.c (apply_ipa_transforms): Inline into only caller ... + (execute_one_pass): ... here. Properly bring in function + bodies for nodes we want to apply IPA transforms to. + +2014-04-24 Jakub Jelinek + + * tree.h (OMP_CLAUSE_LINEAR_GIMPLE_SEQ): Define. + * gimplify.c (omp_is_private): Change last argument's type to int. + Only diagnose lastprivate if the simd argument is 1, only diagnose + linear if the simd argument is 2. + (gimplify_omp_for): Adjust omp_is_private callers. When adding + lastprivate or private, add the clause to OMP_FOR_CLAUSES. Pass + GOVD_EXPLICIT to omp_add_variable. For simd with collapse == 1 + create OMP_CLAUSE_LINEAR rather than OMP_CLAUSE_PRIVATE for var. + If var != decl and decl is in OMP_CLAUSE_LINEAR, gimplify decl + increment to OMP_CLAUSE_LINEAR_GIMPLE_SEQ. + * omp-low.c (scan_sharing_clauses, lower_lastprivate_clauses): Handle + OMP_CLAUSE_LINEAR_GIMPLE_SEQ. + * tree-nested.c (convert_nonlocal_omp_clauses, + convert_local_omp_clauses): Handle OMP_CLAUSE_LINEAR. + +2014-04-23 Uros Bizjak + + Backport from mainline + 2014-04-21 Uros Bizjak + + PR target/60909 + * config/i386/i386.c (ix86_expand_builtin) + : Use temporary + register for target RTX. + : Ditto. + +2014-04-23 Richard Biener + + PR tree-optimization/60903 + * tree-ssa-loop-im.c (analyze_memory_references): Remove + commented code block. + (execute_sm_if_changed): Properly apply IRREDUCIBLE_LOOP + loop flags to newly created BBs and edges. + +2014-04-23 Nick Clifton + + * config/msp430/msp430.c (msp430_handle_option): Move function + to msp430-common.c + (msp430_option_override): Simplify mcu and mcpu option handling. + (msp430_is_f5_mcu): Rename to msp430_use_f5_series_hwmult. Add + support for -mhwmult command line option. + (has_32bit_hwmult): Rename to use_32bit_hwmult. Add support for + -mhwmult command line option. + (msp430_hwmult_enabled): Delete. + (msp43o_output_labelref): Add support for -mhwmult command line + option. + * config/msp430/msp430.md (mulhisi3, umulhisi3, mulsidi3) + (umulsidi3): Likewise. + * config/msp430/msp430.opt (mmcu): Add Report attribute. + (mcpu, mlarge, msmall): Likewise. + (mhwmult): New option. + * config/msp430/msp430-protos.h (msp430_hwmult_enabled): Remove + prototype. + (msp430_is_f5_mcu): Remove prototype. + (msp430_use_f5_series_hwmult): Add prototype. + * config/msp430/msp430-opts.h: New file. + * common/config/msp430: New directory. + * common/config/msp430/msp430-common.c: New file. + * config.gcc (msp430): Remove target_has_targetm_common. + * doc/invoke.texi: Document -mhwmult command line option. + +2014-04-23 Nick Clifton + + * config/i386/cygwin.h (ENDFILE_SPEC): Include + default-manifest.o if it can be found in the search path. + * config/i386/mingw32.h (ENDFILE_SPEC): Likewise. + +2014-04-23 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR lto/60720 + * lto-streamer-out.c (wrap_refs): New function. + (lto_output): Wrap symbol references in global initializes in + type-preserving MEM_REFs. + +2014-04-23 Richard Biener + + PR middle-end/60895 + * tree-inline.c (declare_return_variable): Use mark_addressable. + +2014-04-23 Richard Biener + + PR middle-end/60891 + * loop-init.c (loop_optimizer_init): Make sure to apply + LOOPS_MAY_HAVE_MULTIPLE_LATCHES before fixing up loops. + +2014-04-22 Michael Meissner + + Backport from mainline + 2014-04-21 Michael Meissner + + PR target/60735 + * config/rs6000/rs6000.md (mov_softfloat32, FMOVE64 case): + If mode is DDmode and TARGET_E500_DOUBLE allow move. + + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Print some + more debug information for E500 if -mdebug=reg. + +2014-04-22 H.J. Lu + + Backport from mainline + 2014-04-22 H.J. Lu + + PR target/60868 + * config/i386/i386.c (ix86_expand_set_or_movmem): Call counter_mode + on count_exp to get mode. + +2014-04-22 Bill Schmidt + + * config/rs6000/vsx.md (vsx_xxmrghw_): Adjust for + little-endian. + (vsx_xxmrglw_): Likewise. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR middle-end/55022 + * fold-const.c (negate_expr_p): Don't negate directional rounding + division. + (fold_negate_expr): Likewise. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR middle-end/60849 + * tree-ssa-propagate.c (valid_gimple_rhs_p): Only allow effective + boolean results for comparisons. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR tree-optimization/60841 + * tree-vect-data-refs.c (vect_analyze_data_refs): Count stmts. + * tree-vect-loop.c (vect_analyze_loop_2): Pass down number + of stmts to SLP build. + * tree-vect-slp.c (vect_slp_analyze_bb_1): Likewise. + (vect_analyze_slp): Likewise. + (vect_analyze_slp_instance): Likewise. + (vect_build_slp_tree): Limit overall SLP tree growth. + * tree-vectorizer.h (vect_analyze_data_refs, + vect_analyze_slp): Adjust prototypes. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR tree-optimization/60836 + * tree-vect-loop.c (vect_create_epilog_for_reduction): Force + initial PHI args to be gimple values. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR tree-optimization/59817 + PR tree-optimization/60453 + * graphite-scop-detection.c (graphite_can_represent_scev): Complete + recursion to catch all CHRECs in the scalar evolution and restrict + the predicate for the remains appropriately. + +2014-04-22 Jakub Jelinek + + PR tree-optimization/60823 + * omp-low.c (ipa_simd_modify_function_body): Go through + all SSA_NAMEs and for those refering to vector arguments + which are going to be replaced adjust SSA_NAME_VAR and, + if it is a default definition, change it into a non-default + definition assigned at the beginning of function from new_decl. + (ipa_simd_modify_stmt_ops): Rewritten. + * tree-dfa.c (set_ssa_default_def): When removing default def, + check for NULL loc instead of NULL *loc. + +2014-04-22 Lin Zuojian + + PR middle-end/60281 + * asan.c (asan_emit_stack_protection): Force the base to align to + appropriate bits if STRICT_ALIGNMENT. Set shadow_mem align to + appropriate bits if STRICT_ALIGNMENT. + * cfgexpand.c (expand_stack_vars): Set base_align appropriately + when asan is on. + (expand_used_vars): Leave a space in the stack frame for alignment + if STRICT_ALIGNMENT. + +2014-04-22 Jakub Jelinek + + Backported from mainline + 2014-04-16 Jakub Jelinek + + PR tree-optimization/60844 + * tree-ssa-reassoc.c (reassoc_remove_stmt): New function. + (propagate_op_to_single_use, remove_visited_stmt_chain, + linearize_expr, repropagate_negates, reassociate_bb): Use it + instead of gsi_remove. + +2014-04-22 Jakub Jelinek + + * BASE-VER: Set to 4.9.1. + * DEV-PHASE: Set to prerelease. + 2014-04-22 Release Manager * GCC 4.9.0 released. @@ -59,8 +702,7 @@ 2014-04-11 Tobias Burnus PR other/59055 - * doc/bugreport.texi (Bugs): Remove nodes pointing to the - nirvana. + * doc/bugreport.texi (Bugs): Remove nodes pointing to the nirvana. * doc/gcc.texi (Service): Update description in the @menu * doc/invoke.texi (Option Summary): Remove misplaced and duplicated @menu. @@ -86,15 +728,14 @@ 2014-04-11 Jakub Jelinek PR rtl-optimization/60663 - * cse.c (cse_insn): Set src_volatile on ASM_OPERANDS in - PARALLEL. + * cse.c (cse_insn): Set src_volatile on ASM_OPERANDS in PARALLEL. 2014-04-10 Jan Hubicka Jakub Jelinek PR lto/60567 - * ipa.c (function_and_variable_visibility): Copy forced_by_abi flag from - decl_node to node. + * ipa.c (function_and_variable_visibility): Copy forced_by_abi + flag from decl_node to node. 2014-04-10 Ramana Radhakrishnan @@ -212,9 +853,10 @@ 2014-04-05 Pitchumani Sivanupandi - * config/avr/avr-arch.h (avr_mcu_t): Add dev_attribute field to have device - specific ISA/ feature information. Remove short_sp and errata_skip ds. - Add avr_device_specific_features enum to have device specific info. + * config/avr/avr-arch.h (avr_mcu_t): Add dev_attribute field to have + device specific ISA/ feature information. Remove short_sp and + errata_skip ds. Add avr_device_specific_features enum to have device + specific info. * config/avr/avr-c.c (avr_cpu_cpp_builtins): use dev_attribute to check errata_skip. Add __AVR_ISA_RMW__ builtin macro if RMW ISA available. * config/avr/avr-devices.c (avr_mcu_types): Update AVR_MCU macro for @@ -282,21 +924,21 @@ 2014-04-04 Martin Jambor PR ipa/60640 - * cgraph.h (cgraph_clone_node): New parameter added to declaration. - Adjust all callers. + * cgraph.h (cgraph_clone_node): New parameter added to declaration. + Adjust all callers. * cgraph.c (clone_of_p): Also return true if thunks match. (verify_edge_corresponds_to_fndecl): Removed extraneous call to cgraph_function_or_thunk_node and an obsolete comment. - * cgraphclones.c (build_function_type_skip_args): Moved upwards in the - file. - (build_function_decl_skip_args): Likewise. + * cgraphclones.c (build_function_type_skip_args): Moved upwards in the + file. + (build_function_decl_skip_args): Likewise. (set_new_clone_decl_and_node_flags): New function. - (duplicate_thunk_for_node): Likewise. - (redirect_edge_duplicating_thunks): Likewise. - (cgraph_clone_node): New parameter args_to_skip, pass it to - redirect_edge_duplicating_thunks which is called instead of - cgraph_redirect_edge_callee. - (cgraph_create_virtual_clone): Pass args_to_skip to cgraph_clone_node, + (duplicate_thunk_for_node): Likewise. + (redirect_edge_duplicating_thunks): Likewise. + (cgraph_clone_node): New parameter args_to_skip, pass it to + redirect_edge_duplicating_thunks which is called instead of + cgraph_redirect_edge_callee. + (cgraph_create_virtual_clone): Pass args_to_skip to cgraph_clone_node, moved setting of a lot of flags to set_new_clone_decl_and_node_flags. 2014-04-04 Jeff Law @@ -334,8 +976,8 @@ PR tree-optimization/60505 * tree-vectorizer.h (struct _stmt_vec_info): Add th field as the - threshold of number of iterations below which no vectorization will be - done. + threshold of number of iterations below which no vectorization + will be done. * tree-vect-loop.c (new_loop_vec_info): Initialize LOOP_VINFO_COST_MODEL_THRESHOLD. * tree-vect-loop.c (vect_analyze_loop_operations): @@ -347,8 +989,7 @@ 2014-04-03 Richard Biener - * tree-streamer.h (struct streamer_tree_cache_d): Add next_idx - member. + * tree-streamer.h (struct streamer_tree_cache_d): Add next_idx member. (streamer_tree_cache_create): Adjust. * tree-streamer.c (streamer_tree_cache_add_to_node_array): Adjust to allow optional nodes array. @@ -359,8 +1000,7 @@ * lto-streamer-out.c (create_output_block): Avoid maintaining the node array in the writer cache. (DFS_write_tree): Remove assertion. - (produce_asm_for_decls): Free the out decl state hash table - early. + (produce_asm_for_decls): Free the out decl state hash table early. * lto-streamer-in.c (lto_data_in_create): Adjust for streamer_tree_cache_create prototype change. @@ -381,24 +1021,6 @@ (Weffc++): Remove Scott's numbering, merge lists and reference Wnon-virtual-dtor. - c-family/ - - cp/ - * class.c (accessible_nvdtor_p): New. - (check_bases): Don't check base destructor here ... - (check_bases_and_members): ... check them here. Trigger on - Wnon-virtual-dtor flag. - (finish_struct_1): Use accessible_nvdtor_p. - - testsuite/ - * g++.dg/warn/Wnvdtor.C: Add non-polymorphic case. - * g++.dg/warn/Wnvdtor-2.C: New. - * g++.dg/warn/Wnvdtor-3.C: New. - * g++.dg/warn/Wnvdtor-4.C: New. - * g++.dg/warn/Weff1.C: Delete. - * g++.old-deja/g++.benjamin/15309-1.C: Delete. - * g++.old-deja/g++.benjamin/15309-2.C: Delete. - 2014-04-03 Nick Clifton * config/rl78/rl78-expand.md (movqi): Handle (SUBREG (SYMBOL_REF)) @@ -414,8 +1036,8 @@ 2014-04-02 Jan Hubicka PR ipa/60659 - * ipa-devirt.c (get_polymorphic_call_info): Do not ICE on type inconsistent - code and instead mark the context inconsistent. + * ipa-devirt.c (get_polymorphic_call_info): Do not ICE on type + inconsistent code and instead mark the context inconsistent. (possible_polymorphic_call_targets): For inconsistent contexts return empty complete list. @@ -519,8 +1141,7 @@ 2014-04-01 Richard Biener - * gimple.h (struct gimple_statement_base): Align subcode to - 16 bits. + * gimple.h (struct gimple_statement_base): Align subcode to 16 bits. 2014-04-01 Sebastian Huber diff --git a/gcc-4.9/gcc/DATESTAMP b/gcc-4.9/gcc/DATESTAMP index 50894d115..7dfdaab6e 100644 --- a/gcc-4.9/gcc/DATESTAMP +++ b/gcc-4.9/gcc/DATESTAMP @@ -1 +1 @@ -20140422 +20140514 diff --git a/gcc-4.9/gcc/DEV-PHASE b/gcc-4.9/gcc/DEV-PHASE index e69de29bb..373fbc60b 100644 --- a/gcc-4.9/gcc/DEV-PHASE +++ b/gcc-4.9/gcc/DEV-PHASE @@ -0,0 +1 @@ +prerelease diff --git a/gcc-4.9/gcc/asan.c b/gcc-4.9/gcc/asan.c index 53992a81b..28a476fe4 100644 --- a/gcc-4.9/gcc/asan.c +++ b/gcc-4.9/gcc/asan.c @@ -1017,8 +1017,17 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, base_align_bias = ((asan_frame_size + alignb - 1) & ~(alignb - HOST_WIDE_INT_1)) - asan_frame_size; } + /* Align base if target is STRICT_ALIGNMENT. */ + if (STRICT_ALIGNMENT) + base = expand_binop (Pmode, and_optab, base, + gen_int_mode (-((GET_MODE_ALIGNMENT (SImode) + << ASAN_SHADOW_SHIFT) + / BITS_PER_UNIT), Pmode), NULL_RTX, + 1, OPTAB_DIRECT); + if (use_after_return_class == -1 && pbase) emit_move_insn (pbase, base); + base = expand_binop (Pmode, add_optab, base, gen_int_mode (base_offset - base_align_bias, Pmode), NULL_RTX, 1, OPTAB_DIRECT); @@ -1097,6 +1106,8 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4); shadow_mem = gen_rtx_MEM (SImode, shadow_base); set_mem_alias_set (shadow_mem, asan_shadow_set); + if (STRICT_ALIGNMENT) + set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode))); prev_offset = base_offset; for (l = length; l; l -= 2) { @@ -1186,6 +1197,10 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, shadow_mem = gen_rtx_MEM (BLKmode, shadow_base); set_mem_alias_set (shadow_mem, asan_shadow_set); + + if (STRICT_ALIGNMENT) + set_mem_align (shadow_mem, (GET_MODE_ALIGNMENT (SImode))); + prev_offset = base_offset; last_offset = base_offset; last_size = 0; diff --git a/gcc-4.9/gcc/c-family/ChangeLog b/gcc-4.9/gcc/c-family/ChangeLog index 805ba9ca8..4f277de68 100644 --- a/gcc-4.9/gcc/c-family/ChangeLog +++ b/gcc-4.9/gcc/c-family/ChangeLog @@ -1,3 +1,19 @@ +2014-05-06 Richard Biener + + * c-opts.c (c_common_post_options): For -freestanding, + -fno-hosted and -fno-builtin disable pattern recognition + if not enabled explicitely. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + Marc Glisse + + PR c/60819 + * c-common.c (convert_vector_to_pointer_for_subscript): Properly + apply may-alias the scalar pointer type when applicable. + 2014-04-22 Release Manager * GCC 4.9.0 released. diff --git a/gcc-4.9/gcc/c-family/c-common.c b/gcc-4.9/gcc/c-family/c-common.c index 03731b4b8..f7f2bb3e3 100644 --- a/gcc-4.9/gcc/c-family/c-common.c +++ b/gcc-4.9/gcc/c-family/c-common.c @@ -11770,8 +11770,21 @@ convert_vector_to_pointer_for_subscript (location_t loc, c_common_mark_addressable_vec (*vecp); type = build_qualified_type (TREE_TYPE (type), TYPE_QUALS (type)); - type = build_pointer_type (type); type1 = build_pointer_type (TREE_TYPE (*vecp)); + bool ref_all = TYPE_REF_CAN_ALIAS_ALL (type1); + if (!ref_all + && !DECL_P (*vecp)) + { + /* If the original vector isn't declared may_alias and it + isn't a bare vector look if the subscripting would + alias the vector we subscript, and if not, force ref-all. */ + alias_set_type vecset = get_alias_set (*vecp); + alias_set_type sset = get_alias_set (type); + if (!alias_sets_must_conflict_p (sset, vecset) + && !alias_set_subset_of (sset, vecset)) + ref_all = true; + } + type = build_pointer_type_for_mode (type, ptr_mode, ref_all); *vecp = build1 (ADDR_EXPR, type1, *vecp); *vecp = convert (type, *vecp); } diff --git a/gcc-4.9/gcc/c-family/c-opts.c b/gcc-4.9/gcc/c-family/c-opts.c index e162e49a1..29e9a355b 100644 --- a/gcc-4.9/gcc/c-family/c-opts.c +++ b/gcc-4.9/gcc/c-family/c-opts.c @@ -851,6 +851,12 @@ c_common_post_options (const char **pfilename) if (flag_objc_exceptions && !flag_objc_sjlj_exceptions) flag_exceptions = 1; + /* If -ffreestanding, -fno-hosted or -fno-builtin then disable + pattern recognition. */ + if (!global_options_set.x_flag_tree_loop_distribute_patterns + && flag_no_builtin) + flag_tree_loop_distribute_patterns = 0; + /* -Woverlength-strings is off by default, but is enabled by -Wpedantic. It is never enabled in C++, as the minimum limit is not normative in that standard. */ diff --git a/gcc-4.9/gcc/c/ChangeLog b/gcc-4.9/gcc/c/ChangeLog index f5e7179e9..5f4a207a7 100644 --- a/gcc-4.9/gcc/c/ChangeLog +++ b/gcc-4.9/gcc/c/ChangeLog @@ -1,3 +1,15 @@ +2014-04-24 Jakub Jelinek + + * c-parser.c (c_parser_omp_atomic): Allow seq_cst before + atomic-clause, allow comma in between atomic-clause and + seq_cst. + +2014-04-22 Jakub Jelinek + + PR c/59073 + * c-parser.c (c_parser_omp_parallel): If c_parser_omp_for + fails, don't set OM_PARALLEL_COMBINED and return NULL. + 2014-04-22 Release Manager * GCC 4.9.0 released. diff --git a/gcc-4.9/gcc/c/c-parser.c b/gcc-4.9/gcc/c/c-parser.c index 5653e49f4..6eb235c5c 100644 --- a/gcc-4.9/gcc/c/c-parser.c +++ b/gcc-4.9/gcc/c/c-parser.c @@ -11195,6 +11195,18 @@ c_parser_omp_atomic (location_t loc, c_parser *parser) bool swapped = false; bool seq_cst = false; + if (c_parser_next_token_is (parser, CPP_NAME)) + { + const char *p = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value); + if (!strcmp (p, "seq_cst")) + { + seq_cst = true; + c_parser_consume_token (parser); + if (c_parser_next_token_is (parser, CPP_COMMA) + && c_parser_peek_2nd_token (parser)->type == CPP_NAME) + c_parser_consume_token (parser); + } + } if (c_parser_next_token_is (parser, CPP_NAME)) { const char *p = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value); @@ -11212,13 +11224,21 @@ c_parser_omp_atomic (location_t loc, c_parser *parser) if (p) c_parser_consume_token (parser); } - if (c_parser_next_token_is (parser, CPP_NAME)) + if (!seq_cst) { - const char *p = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value); - if (!strcmp (p, "seq_cst")) + if (c_parser_next_token_is (parser, CPP_COMMA) + && c_parser_peek_2nd_token (parser)->type == CPP_NAME) + c_parser_consume_token (parser); + + if (c_parser_next_token_is (parser, CPP_NAME)) { - seq_cst = true; - c_parser_consume_token (parser); + const char *p + = IDENTIFIER_POINTER (c_parser_peek_token (parser)->value); + if (!strcmp (p, "seq_cst")) + { + seq_cst = true; + c_parser_consume_token (parser); + } } } c_parser_skip_to_pragma_eol (parser); @@ -12208,10 +12228,12 @@ c_parser_omp_parallel (location_t loc, c_parser *parser, if (!flag_openmp) /* flag_openmp_simd */ return c_parser_omp_for (loc, parser, p_name, mask, cclauses); block = c_begin_omp_parallel (); - c_parser_omp_for (loc, parser, p_name, mask, cclauses); + tree ret = c_parser_omp_for (loc, parser, p_name, mask, cclauses); stmt = c_finish_omp_parallel (loc, cclauses[C_OMP_CLAUSE_SPLIT_PARALLEL], block); + if (ret == NULL_TREE) + return ret; OMP_PARALLEL_COMBINED (stmt) = 1; return stmt; } diff --git a/gcc-4.9/gcc/cfgexpand.c b/gcc-4.9/gcc/cfgexpand.c index b7f63602d..14511e137 100644 --- a/gcc-4.9/gcc/cfgexpand.c +++ b/gcc-4.9/gcc/cfgexpand.c @@ -1013,10 +1013,19 @@ expand_stack_vars (bool (*pred) (size_t), struct stack_vars_data *data) if (data->asan_base == NULL) data->asan_base = gen_reg_rtx (Pmode); base = data->asan_base; + + if (!STRICT_ALIGNMENT) + base_align = crtl->max_used_stack_slot_alignment; + else + base_align = MAX (crtl->max_used_stack_slot_alignment, + GET_MODE_ALIGNMENT (SImode) + << ASAN_SHADOW_SHIFT); } else - offset = alloc_stack_frame_space (stack_vars[i].size, alignb); - base_align = crtl->max_used_stack_slot_alignment; + { + offset = alloc_stack_frame_space (stack_vars[i].size, alignb); + base_align = crtl->max_used_stack_slot_alignment; + } } else { @@ -1845,6 +1854,11 @@ expand_used_vars (void) = alloc_stack_frame_space (redzonesz, ASAN_RED_ZONE_SIZE); data.asan_vec.safe_push (prev_offset); data.asan_vec.safe_push (offset); + /* Leave space for alignment if STRICT_ALIGNMENT. */ + if (STRICT_ALIGNMENT) + alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode) + << ASAN_SHADOW_SHIFT) + / BITS_PER_UNIT, 1); var_end_seq = asan_emit_stack_protection (virtual_stack_vars_rtx, diff --git a/gcc-4.9/gcc/config.gcc b/gcc-4.9/gcc/config.gcc index 2ad81ea91..04681224f 100644 --- a/gcc-4.9/gcc/config.gcc +++ b/gcc-4.9/gcc/config.gcc @@ -2146,7 +2146,6 @@ msp430*-*-*) tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}" c_target_objs="msp430-c.o" cxx_target_objs="msp430-c.o" - target_has_targetm_common=no tmake_file="${tmake_file} msp430/t-msp430" ;; nds32le-*-*) diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.h b/gcc-4.9/gcc/config/aarch64/aarch64.h index 7962aa472..2fd6df4af 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.h +++ b/gcc-4.9/gcc/config/aarch64/aarch64.h @@ -32,7 +32,7 @@ else \ builtin_define ("__AARCH64EL__"); \ \ - if (!TARGET_GENERAL_REGS_ONLY) \ + if (TARGET_SIMD) \ builtin_define ("__ARM_NEON"); \ \ switch (aarch64_cmodel) \ @@ -83,9 +83,9 @@ #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) /* AdvSIMD is supported in the default configuration, unless disabled by - -mgeneral-regs-only. */ -#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY -#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY + -mgeneral-regs-only or by the +nosimd extension. */ +#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) +#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) #define UNITS_PER_WORD 8 @@ -185,8 +185,8 @@ extern unsigned long aarch64_isa_flags; extern unsigned long aarch64_tune_flags; #define AARCH64_TUNE_SLOWMUL (aarch64_tune_flags & AARCH64_FL_SLOWMUL) -/* Crypto is an optional feature. */ -#define TARGET_CRYPTO AARCH64_ISA_CRYPTO +/* Crypto is an optional extension to AdvSIMD. */ +#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) /* Standard register usage. */ diff --git a/gcc-4.9/gcc/config/alpha/alpha.c b/gcc-4.9/gcc/config/alpha/alpha.c index df4cc1b1c..dc07a02c0 100644 --- a/gcc-4.9/gcc/config/alpha/alpha.c +++ b/gcc-4.9/gcc/config/alpha/alpha.c @@ -62,6 +62,7 @@ along with GCC; see the file COPYING3. If not see #include "gimple-expr.h" #include "is-a.h" #include "gimple.h" +#include "gimple-iterator.h" #include "gimplify.h" #include "gimple-ssa.h" #include "stringpool.h" @@ -7042,9 +7043,6 @@ alpha_fold_builtin (tree fndecl, int n_args, tree *op, case ALPHA_BUILTIN_MSKQH: return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, true); - case ALPHA_BUILTIN_UMULH: - return fold_build2 (MULT_HIGHPART_EXPR, alpha_dimode_u, op[0], op[1]); - case ALPHA_BUILTIN_ZAP: opint[1] ^= 0xff; /* FALLTHRU */ @@ -7094,6 +7092,49 @@ alpha_fold_builtin (tree fndecl, int n_args, tree *op, return NULL; } } + +bool +alpha_gimple_fold_builtin (gimple_stmt_iterator *gsi) +{ + bool changed = false; + gimple stmt = gsi_stmt (*gsi); + tree call = gimple_call_fn (stmt); + gimple new_stmt = NULL; + + if (call) + { + tree fndecl = gimple_call_fndecl (stmt); + + if (fndecl) + { + tree arg0, arg1; + + switch (DECL_FUNCTION_CODE (fndecl)) + { + case ALPHA_BUILTIN_UMULH: + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + + new_stmt + = gimple_build_assign_with_ops (MULT_HIGHPART_EXPR, + gimple_call_lhs (stmt), + arg0, + arg1); + break; + default: + break; + } + } + } + + if (new_stmt) + { + gsi_replace (gsi, new_stmt, true); + changed = true; + } + + return changed; +} /* This page contains routines that are used to determine what the function prologue and epilogue code will do and write them out. */ @@ -9790,6 +9831,8 @@ alpha_canonicalize_comparison (int *code, rtx *op0, rtx *op1, #define TARGET_EXPAND_BUILTIN alpha_expand_builtin #undef TARGET_FOLD_BUILTIN #define TARGET_FOLD_BUILTIN alpha_fold_builtin +#undef TARGET_GIMPLE_FOLD_BUILTIN +#define TARGET_GIMPLE_FOLD_BUILTIN alpha_gimple_fold_builtin #undef TARGET_FUNCTION_OK_FOR_SIBCALL #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall diff --git a/gcc-4.9/gcc/config/avr/avr-mcus.def b/gcc-4.9/gcc/config/avr/avr-mcus.def index 3cf2fcd41..483a30321 100644 --- a/gcc-4.9/gcc/config/avr/avr-mcus.def +++ b/gcc-4.9/gcc/config/avr/avr-mcus.def @@ -291,7 +291,7 @@ AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192A3__ AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192D3__", 0x2000, 4, "x192d3") AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3__", 0x2000, 5, "x256a3") AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3B__", 0x2000, 5, "x256a3b") -AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega258A3BU__", 0x2000, 5, "x256a3bu") +AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3BU__", 0x2000, 5, "x256a3bu") AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256D3__", 0x2000, 5, "x256d3") AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128A3U__", 0x2000, 3, "x128a3u") AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B1__", 0x2000, 3, "x128b1") diff --git a/gcc-4.9/gcc/config/avr/avr.c b/gcc-4.9/gcc/config/avr/avr.c index 99644ec92..fa979df46 100644 --- a/gcc-4.9/gcc/config/avr/avr.c +++ b/gcc-4.9/gcc/config/avr/avr.c @@ -2353,6 +2353,12 @@ avr_notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn) } break; + case CC_SET_VZN: + /* Insn like INC, DEC, NEG that set Z,N,V. We currently don't make use + of this combination, cf. also PR61055. */ + CC_STATUS_INIT; + break; + case CC_SET_CZN: /* Insn sets the Z,N,C flags of CC to recog_operand[0]. The V flag may or may not be known but that's ok because @@ -3987,7 +3993,7 @@ avr_out_store_psi (rtx insn, rtx *op, int *plen) "std Y+61,%A1" CR_TAB "std Y+62,%B1" CR_TAB "std Y+63,%C1" CR_TAB - "sbiw r28,%o0-60", op, plen, -5); + "sbiw r28,%o0-61", op, plen, -5); return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB "sbci r29,hi8(-%o0)" CR_TAB @@ -6284,7 +6290,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, if (REG_P (xop[2])) { - *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_SET_N; + *pcc = MINUS == code ? (int) CC_SET_CZN : (int) CC_CLOBBER; for (i = 0; i < n_bytes; i++) { @@ -6393,7 +6399,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, op, plen, 1); if (n_bytes == 2 && PLUS == code) - *pcc = CC_SET_ZN; + *pcc = CC_SET_CZN; } i++; @@ -6416,6 +6422,7 @@ avr_out_plus_1 (rtx *xop, int *plen, enum rtx_code code, int *pcc, { avr_asm_len ((code == PLUS) ^ (val8 == 1) ? "dec %0" : "inc %0", op, plen, 1); + *pcc = CC_CLOBBER; break; } diff --git a/gcc-4.9/gcc/config/avr/avr.md b/gcc-4.9/gcc/config/avr/avr.md index d7baa4a83..2c59bf3f9 100644 --- a/gcc-4.9/gcc/config/avr/avr.md +++ b/gcc-4.9/gcc/config/avr/avr.md @@ -90,7 +90,7 @@ (include "constraints.md") ;; Condition code settings. -(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber, +(define_attr "cc" "none,set_czn,set_zn,set_vzn,set_n,compare,clobber, plus,ldi" (const_string "none")) @@ -1098,7 +1098,7 @@ inc %0\;inc %0 dec %0\;dec %0" [(set_attr "length" "1,1,1,1,2,2") - (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")]) + (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")]) ;; "addhi3" ;; "addhq3" "adduhq3" @@ -1369,7 +1369,7 @@ dec %0\;dec %0 inc %0\;inc %0" [(set_attr "length" "1,1,1,1,2,2") - (set_attr "cc" "set_czn,set_czn,set_zn,set_zn,set_zn,set_zn")]) + (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")]) ;; "subhi3" ;; "subhq3" "subuhq3" @@ -3992,7 +3992,7 @@ "" "neg %0" [(set_attr "length" "1") - (set_attr "cc" "set_zn")]) + (set_attr "cc" "set_vzn")]) (define_insn "*negqihi2" [(set (match_operand:HI 0 "register_operand" "=r") diff --git a/gcc-4.9/gcc/config/i386/cygwin.h b/gcc-4.9/gcc/config/i386/cygwin.h index f7b9a284c..165d3aae2 100644 --- a/gcc-4.9/gcc/config/i386/cygwin.h +++ b/gcc-4.9/gcc/config/i386/cygwin.h @@ -45,6 +45,7 @@ along with GCC; see the file COPYING3. If not see #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}\ + %{!shared:%:if-exists(default-manifest.o%s)}\ crtend.o%s" /* Normally, -lgcc is not needed since everything in it is in the DLL, but we diff --git a/gcc-4.9/gcc/config/i386/i386.c b/gcc-4.9/gcc/config/i386/i386.c index 3eefe4ac5..d7c592f48 100644 --- a/gcc-4.9/gcc/config/i386/i386.c +++ b/gcc-4.9/gcc/config/i386/i386.c @@ -3128,7 +3128,7 @@ ix86_option_override_internal (bool main_args_p, (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C) #define PTA_HASWELL \ (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \ - | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE) + | PTA_FMA | PTA_MOVBE | PTA_HLE) #define PTA_BROADWELL \ (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED) #define PTA_BONNELL \ @@ -24151,8 +24151,13 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, align = MEM_ALIGN (dst) / BITS_PER_UNIT; if (CONST_INT_P (count_exp)) - min_size = max_size = probable_max_size = count = expected_size - = INTVAL (count_exp); + { + min_size = max_size = probable_max_size = count = expected_size + = INTVAL (count_exp); + /* When COUNT is 0, there is nothing to do. */ + if (!count) + return true; + } else { if (min_size_exp) @@ -24161,7 +24166,7 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, max_size = INTVAL (max_size_exp); if (probable_max_size_exp) probable_max_size = INTVAL (probable_max_size_exp); - if (CONST_INT_P (expected_size_exp) && count == 0) + if (CONST_INT_P (expected_size_exp)) expected_size = INTVAL (expected_size_exp); } @@ -24390,7 +24395,8 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, if (jump_around_label == NULL_RTX) jump_around_label = gen_label_rtx (); emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1), - LEU, 0, GET_MODE (count_exp), 1, hot_label); + LEU, 0, counter_mode (count_exp), + 1, hot_label); predict_jump (REG_BR_PROB_BASE * 90 / 100); if (issetmem) set_storage_via_libcall (dst, count_exp, val_exp, false); @@ -35406,7 +35412,8 @@ rdrand_step: else op2 = gen_rtx_SUBREG (SImode, op0, 0); - if (target == 0) + if (target == 0 + || !register_operand (target, SImode)) target = gen_reg_rtx (SImode); pat = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), @@ -35448,7 +35455,8 @@ rdseed_step: const0_rtx); emit_insn (gen_rtx_SET (VOIDmode, op2, pat)); - if (target == 0) + if (target == 0 + || !register_operand (target, SImode)) target = gen_reg_rtx (SImode); emit_insn (gen_zero_extendqisi2 (target, op2)); diff --git a/gcc-4.9/gcc/config/i386/i386.md b/gcc-4.9/gcc/config/i386/i386.md index 25e2e93e3..9f103cf30 100644 --- a/gcc-4.9/gcc/config/i386/i386.md +++ b/gcc-4.9/gcc/config/i386/i386.md @@ -14427,15 +14427,16 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { + rtx tmp1, tmp2; if (optimize_insn_for_size_p ()) FAIL; - operands[3] = gen_reg_rtx (XFmode); - operands[4] = gen_reg_rtx (XFmode); + tmp1 = gen_reg_rtx (XFmode); + tmp2 = gen_reg_rtx (XFmode); - emit_insn (gen_floatsixf2 (operands[3], operands[2])); - emit_insn (gen_fscalexf4_i387 (operands[0], operands[4], - operands[1], operands[3])); + emit_insn (gen_floatsixf2 (tmp1, operands[2])); + emit_insn (gen_fscalexf4_i387 (operands[0], tmp2, + operands[1], tmp1)); DONE; }) diff --git a/gcc-4.9/gcc/config/i386/mingw32.h b/gcc-4.9/gcc/config/i386/mingw32.h index f56382095..4cfd5f013 100644 --- a/gcc-4.9/gcc/config/i386/mingw32.h +++ b/gcc-4.9/gcc/config/i386/mingw32.h @@ -148,6 +148,7 @@ along with GCC; see the file COPYING3. If not see #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ + %{!shared:%:if-exists(default-manifest.o%s)}\ crtend.o%s" /* Override startfile prefix defaults. */ diff --git a/gcc-4.9/gcc/config/msp430/msp430-protos.h b/gcc-4.9/gcc/config/msp430/msp430-protos.h index 7f999abbd..f0b8aea03 100644 --- a/gcc-4.9/gcc/config/msp430/msp430-protos.h +++ b/gcc-4.9/gcc/config/msp430/msp430-protos.h @@ -30,11 +30,9 @@ const char * msp430x_extendhisi (rtx *); void msp430_fixup_compare_operands (enum machine_mode, rtx *); int msp430_hard_regno_mode_ok (int, enum machine_mode); int msp430_hard_regno_nregs (int, enum machine_mode); -bool msp430_hwmult_enabled (void); rtx msp430_incoming_return_addr_rtx (void); void msp430_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); int msp430_initial_elimination_offset (int, int); -bool msp430_is_f5_mcu (void); bool msp430_is_interrupt_func (void); const char * msp430x_logical_shift_right (rtx); const char * msp430_mcu_name (void); @@ -45,5 +43,6 @@ rtx msp430_return_addr_rtx (int); void msp430_split_movsi (rtx *); void msp430_start_function (FILE *, const char *, tree); rtx msp430_subreg (enum machine_mode, rtx, enum machine_mode, int); +bool msp430_use_f5_series_hwmult (void); #endif /* GCC_MSP430_PROTOS_H */ diff --git a/gcc-4.9/gcc/config/msp430/msp430.c b/gcc-4.9/gcc/config/msp430/msp430.c index 80a17a6e3..c844aa2a1 100644 --- a/gcc-4.9/gcc/config/msp430/msp430.c +++ b/gcc-4.9/gcc/config/msp430/msp430.c @@ -95,18 +95,6 @@ msp430_init_machine_status (void) return m; } -#undef TARGET_HANDLE_OPTION -#define TARGET_HANDLE_OPTION msp430_handle_option - -bool -msp430_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED, - struct gcc_options *opts_set ATTRIBUTE_UNUSED, - const struct cl_decoded_option *decoded ATTRIBUTE_UNUSED, - location_t loc ATTRIBUTE_UNUSED) -{ - return true; -} - #undef TARGET_OPTION_OVERRIDE #define TARGET_OPTION_OVERRIDE msp430_option_override @@ -196,19 +184,14 @@ msp430_option_override (void) if (target_cpu) { - if (strcasecmp (target_cpu, "msp430x") == 0 - || strcasecmp (target_cpu, "msp430xv2") == 0 - || strcasecmp (target_cpu, "430x") == 0 - || strcasecmp (target_cpu, "430xv2") == 0) + if (strcasecmp (target_cpu, "msp430x") == 0) msp430x = true; - else if (strcasecmp (target_cpu, "msp430") == 0 - || strcasecmp (target_cpu, "430") == 0) + else /* target_cpu == "msp430" - already handled by the front end. */ msp430x = false; - else - error ("unrecognised argument of -mcpu: %s", target_cpu); } - - if (target_mcu) + /* Note - the front end has already ensured at most + one of target_cpu and target_mcu will be set. */ + else if (target_mcu) { int i; @@ -217,25 +200,12 @@ msp430_option_override (void) supports 430. */ msp430x = true; - /* For backwards compatibility we recognise two generic MCU - 430X names. However we want to be able to generate special C - preprocessor defines for them, which is why we set target_mcu - to NULL. */ - if (strcasecmp (target_mcu, "msp430") == 0) - { - msp430x = false; - target_mcu = NULL; - } - else if (strcasecmp (target_mcu, "msp430x") == 0 - || strcasecmp (target_mcu, "msp430xv2") == 0) - target_mcu = NULL; - else - for (i = ARRAY_SIZE (msp430_mcu_names); i--;) - if (strcasecmp (msp430_mcu_names[i], target_mcu) == 0) - { - msp430x = false; - break; - } + for (i = ARRAY_SIZE (msp430_mcu_names); i--;) + if (strcasecmp (msp430_mcu_names[i], target_mcu) == 0) + { + msp430x = false; + break; + } /* It is not an error if we do not match the MCU name. There are hundreds of them. */ } @@ -1847,16 +1817,20 @@ static const struct /* Returns true if the current MCU is an F5xxx series. */ bool -msp430_is_f5_mcu (void) +msp430_use_f5_series_hwmult (void) { - if (target_mcu == NULL) + if (msp430_hwmult_type == F5SERIES) + return true; + + if (target_mcu == NULL || msp430_hwmult_type != AUTO) return false; + return strncasecmp (target_mcu, "msp430f5", 8) == 0; } /* Returns true id the current MCU has a second generation 32-bit hardware multiplier. */ static bool -has_32bit_hw_mult (void) +use_32bit_hwmult (void) { static const char * known_32bit_mult_mcus [] = { @@ -1868,7 +1842,11 @@ has_32bit_hw_mult (void) "msp430f47177", "msp430f47187", "msp430f47197" }; int i; - if (target_mcu == NULL) + + if (msp430_hwmult_type == LARGE) + return true; + + if (target_mcu == NULL || msp430_hwmult_type != AUTO) return false; for (i = ARRAY_SIZE (known_32bit_mult_mcus); i--;) @@ -1878,25 +1856,6 @@ has_32bit_hw_mult (void) return false; } -/* Returns true if hardware multiply is supported by the chosen MCU. */ -bool -msp430_hwmult_enabled (void) -{ - if (target_mcu == NULL) - return false; - - if (!ENABLE_HWMULT) - return false; - - if (msp430_is_interrupt_func ()) - return false; - - if (msp430_is_f5_mcu () || has_32bit_hw_mult ()) - return true; - - return false; -} - /* This function does the same as the default, but it will replace GCC function names with the MSPABI-specified ones. */ void @@ -1913,20 +1872,20 @@ msp430_output_labelref (FILE *file, const char *name) /* If we have been given a specific MCU name then we may be able to make use of its hardware multiply capabilities. */ - if (msp430_hwmult_enabled ()) + if (msp430_hwmult_type != NONE) { if (strcmp ("__mspabi_mpyi", name) == 0) { - if (msp430_is_f5_mcu ()) + if (msp430_use_f5_series_hwmult ()) name = "__mulhi2_f5"; else name = "__mulhi2"; } else if (strcmp ("__mspabi_mpyl", name) == 0) { - if (msp430_is_f5_mcu ()) + if (msp430_use_f5_series_hwmult ()) name = "__mulsi2_f5"; - else if (has_32bit_hw_mult ()) + else if (use_32bit_hwmult ()) name = "__mulsi2_hw32"; else name = "__mulsi2"; @@ -2203,7 +2162,7 @@ msp430_print_operand (FILE * file, rtx op, int letter) because builtins are expanded before the frame layout is determined. */ fprintf (file, "%d", msp430_initial_elimination_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM) - - 2); + - (TARGET_LARGE ? 4 : 2)); return; case 'J': diff --git a/gcc-4.9/gcc/config/msp430/msp430.md b/gcc-4.9/gcc/config/msp430/msp430.md index c0c97dae6..74a98b480 100644 --- a/gcc-4.9/gcc/config/msp430/msp430.md +++ b/gcc-4.9/gcc/config/msp430/msp430.md @@ -1321,12 +1321,12 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] - "optimize > 2 && msp430_hwmult_enabled ()" + "optimize > 2 && msp430_hwmult_type != NONE" "* - if (msp430_is_f5_mcu ()) - return \"MOV.W %1, &0x04C2 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0\"; + if (msp430_use_f5_series_hwmult ()) + return \"PUSH.W sr { DINT { MOV.W %1, &0x04C2 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0 { POP.W sr\"; else - return \"MOV.W %1, &0x0132 { MOV.W %2, &0x0138 { MOV.W &0x013A, %L0 { MOV.W &0x013C, %H0\"; + return \"PUSH.W sr { DINT { MOV.W %1, &0x0132 { MOV.W %2, &0x0138 { MOV.W &0x013A, %L0 { MOV.W &0x013C, %H0 { POP.W sr\"; " ) @@ -1334,12 +1334,12 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0")) (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] - "optimize > 2 && msp430_hwmult_enabled ()" + "optimize > 2 && msp430_hwmult_type != NONE" "* - if (msp430_is_f5_mcu ()) - return \"MOV.W %1, &0x04C0 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0\"; + if (msp430_use_f5_series_hwmult ()) + return \"PUSH.W sr { DINT { MOV.W %1, &0x04C0 { MOV.W %2, &0x04C8 { MOV.W &0x04CA, %L0 { MOV.W &0x04CC, %H0 { POP.W sr\"; else - return \"MOV.W %1, &0x0130 { MOV.W %2, &0x0138 { MOV.W &0x013A, %L0 { MOV.W &0x013C, %H0\"; + return \"PUSH.W sr { DINT { MOV.W %1, &0x0130 { MOV.W %2, &0x0138 { MOV.W &0x013A, %L0 { MOV.W &0x013C, %H0 { POP.W sr\"; " ) @@ -1347,12 +1347,12 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] - "optimize > 2 && msp430_hwmult_enabled ()" + "optimize > 2 && msp430_hwmult_type != NONE" "* - if (msp430_is_f5_mcu ()) - return \"MOV.W %L1, &0x04D4 { MOV.W %H1, &0x04D6 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0\"; + if (msp430_use_f5_series_hwmult ()) + return \"PUSH.W sr { DINT { MOV.W %L1, &0x04D4 { MOV.W %H1, &0x04D6 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0 { POP.W sr\"; else - return \"MOV.W %L1, &0x0144 { MOV.W %H1, &0x0146 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0\"; + return \"PUSH.W sr { DINT { MOV.W %L1, &0x0144 { MOV.W %H1, &0x0146 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0 { POP.W sr\"; " ) @@ -1360,11 +1360,11 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] - "optimize > 2 && msp430_hwmult_enabled ()" + "optimize > 2 && msp430_hwmult_type != NONE" "* - if (msp430_is_f5_mcu ()) - return \"MOV.W %L1, &0x04D0 { MOV.W %H1, &0x04D2 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0\"; + if (msp430_use_f5_series_hwmult ()) + return \"PUSH.W sr { DINT { MOV.W %L1, &0x04D0 { MOV.W %H1, &0x04D2 { MOV.W %L2, &0x04E0 { MOV.W %H2, &0x04E2 { MOV.W &0x04E4, %A0 { MOV.W &0x04E6, %B0 { MOV.W &0x04E8, %C0 { MOV.W &0x04EA, %D0 { POP.W sr\"; else - return \"MOV.W %L1, &0x0140 { MOV.W %H1, &0x0141 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0\"; + return \"PUSH.W sr { DINT { MOV.W %L1, &0x0140 { MOV.W %H1, &0x0142 { MOV.W %L2, &0x0150 { MOV.W %H2, &0x0152 { MOV.W &0x0154, %A0 { MOV.W &0x0156, %B0 { MOV.W &0x0158, %C0 { MOV.W &0x015A, %D0 { POP.W sr\"; " ) diff --git a/gcc-4.9/gcc/config/msp430/msp430.opt b/gcc-4.9/gcc/config/msp430/msp430.opt index 5a447c0d2..8215013e8 100644 --- a/gcc-4.9/gcc/config/msp430/msp430.opt +++ b/gcc-4.9/gcc/config/msp430/msp430.opt @@ -7,19 +7,19 @@ Target Mask(ASM_HEX) Force assembly output to always use hex constants mmcu= -Target ToLower Joined RejectNegative Var(target_mcu) +Target Report ToLower Joined RejectNegative Var(target_mcu) Specify the MCU to build for. mcpu= -Target Joined RejectNegative Var(target_cpu) +Target Report Joined RejectNegative Var(target_cpu) Specify the ISA to build for: msp430, mdsp430x, msp430xv2 mlarge -Target Mask(LARGE) RejectNegative +Target Report Mask(LARGE) RejectNegative Select large model - 20-bit addresses/pointers msmall -Target InverseMask(LARGE) RejectNegative +Target Report InverseMask(LARGE) RejectNegative Select small model - 16-bit addresses/pointers (default) mrelax @@ -33,6 +33,27 @@ minrt Target Report Mask(MINRT) RejectNegative Use a minimum runtime (no static initializers or ctors) for memory-constrained devices. -mhwmult -Target Report Var(ENABLE_HWMULT, 1) Init(1) -Enable hardware multiply (except in interrupt routines) +HeaderInclude +config/msp430/msp430-opts.h + +mhwmult= +Target Joined RejectNegative Report ToLower Var(msp430_hwmult_type) Enum(msp430_hwmult_types) Init(AUTO) +Specify the type of hardware multiply to support + +Enum +Name(msp430_hwmult_types) Type(enum msp430_hwmult_types) + +EnumValue +Enum(msp430_hwmult_types) String(none) Value(NONE) + +EnumValue +Enum(msp430_hwmult_types) String(auto) Value(AUTO) + +EnumValue +Enum(msp430_hwmult_types) String(16bit) Value(SMALL) + +EnumValue +Enum(msp430_hwmult_types) String(32bit) Value(LARGE) + +EnumValue +Enum(msp430_hwmult_types) String(f5series) Value(F5SERIES) diff --git a/gcc-4.9/gcc/config/rs6000/altivec.md b/gcc-4.9/gcc/config/rs6000/altivec.md index 674cb40bf..a8cfcb739 100644 --- a/gcc-4.9/gcc/config/rs6000/altivec.md +++ b/gcc-4.9/gcc/config/rs6000/altivec.md @@ -143,6 +143,9 @@ UNSPEC_VSUBEUQM UNSPEC_VSUBECUQ UNSPEC_VBPERMQ + UNSPEC_BCDADD + UNSPEC_BCDSUB + UNSPEC_BCD_OVERFLOW ]) (define_c_enum "unspecv" @@ -3334,3 +3337,112 @@ "vbpermq %0,%1,%2" [(set_attr "length" "4") (set_attr "type" "vecsimple")]) + +;; Decimal Integer operations +(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB]) + +(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add") + (UNSPEC_BCDSUB "sub")]) + +(define_code_iterator BCD_TEST [eq lt gt unordered]) + +(define_insn "bcd" + [(set (match_operand:V1TI 0 "register_operand" "") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB)) + (clobber (reg:CCFP 74))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we +;; can use the unordered test for BCD nans and add/subtracts that overflow. An +;; UNORDERED test on an integer type (like V1TImode) is not defined. The type +;; probably should be one that can go in the VMX (Altivec) registers, so we +;; can't use DDmode or DFmode. +(define_insn "*bcd_test" + [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:QI 3 "const_0_to_1_operand" "i")] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" "j"))) + (clobber (match_scratch:V1TI 0 "=v"))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_insn "*bcd_test2" + [(set (match_operand:V1TI 0 "register_operand" "=v") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") + (match_operand:V1TI 2 "register_operand" "v") + (match_operand:QI 3 "const_0_to_1_operand" "i")] + UNSPEC_BCD_ADD_SUB)) + (set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" "j")))] + "TARGET_P8_VECTOR" + "bcd. %0,%1,%2,%3" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +(define_expand "bcd_" + [(parallel [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB) + (match_dup 4))) + (clobber (match_scratch:V1TI 5 ""))]) + (set (match_operand:SI 0 "register_operand" "") + (BCD_TEST:SI (reg:CCFP 74) + (const_int 0)))] + "TARGET_P8_VECTOR" +{ + operands[4] = CONST0_RTX (V2DFmode); +}) + +;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and +;; the bcdadd/bcdsub that tests the value. The combiner won't work since +;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate +;; support is hard coded to use the fixed register CR6 instead of creating +;; a register class for CR6. + +(define_peephole2 + [(parallel [(set (match_operand:V1TI 0 "register_operand" "") + (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") + (match_operand:V1TI 2 "register_operand" "") + (match_operand:QI 3 "const_0_to_1_operand" "")] + UNSPEC_BCD_ADD_SUB)) + (clobber (reg:CCFP 74))]) + (parallel [(set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_operand:V2DF 4 "zero_constant" ""))) + (clobber (match_operand:V1TI 5 "register_operand" ""))])] + "TARGET_P8_VECTOR" + [(parallel [(set (match_dup 0) + (unspec:V1TI [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB)) + (set (reg:CCFP 74) + (compare:CCFP + (unspec:V2DF [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_BCD_ADD_SUB) + (match_dup 4)))])]) diff --git a/gcc-4.9/gcc/config/rs6000/dfp.md b/gcc-4.9/gcc/config/rs6000/dfp.md index 8e99bc0d7..40e27e77d 100644 --- a/gcc-4.9/gcc/config/rs6000/dfp.md +++ b/gcc-4.9/gcc/config/rs6000/dfp.md @@ -322,3 +322,72 @@ "TARGET_DFP" "dctfixq %0,%1" [(set_attr "type" "fp")]) + + +;; Decimal builtin support + +(define_c_enum "unspec" + [UNSPEC_DDEDPD + UNSPEC_DENBCD + UNSPEC_DXEX + UNSPEC_DIEX + UNSPEC_DSCLI + UNSPEC_DSCRI]) + +(define_mode_iterator D64_D128 [DD TD]) + +(define_mode_attr dfp_suffix [(DD "") + (TD "q")]) + +(define_insn "dfp_ddedpd_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DDEDPD))] + "TARGET_DFP" + "ddedpd %1,%0,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_denbcd_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DENBCD))] + "TARGET_DFP" + "denbcd %1,%0,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_dxex_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")] + UNSPEC_DXEX))] + "TARGET_DFP" + "dxex %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "dfp_diex_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:D64_D128 2 "gpc_reg_operand" "d")] + UNSPEC_DXEX))] + "TARGET_DFP" + "diex %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_dscli_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:QI 2 "immediate_operand" "i")] + UNSPEC_DSCLI))] + "TARGET_DFP" + "dscli %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "dfp_dscri_" + [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") + (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") + (match_operand:QI 2 "immediate_operand" "i")] + UNSPEC_DSCRI))] + "TARGET_DFP" + "dscri %0,%1,%2" + [(set_attr "type" "fp")]) diff --git a/gcc-4.9/gcc/config/rs6000/predicates.md b/gcc-4.9/gcc/config/rs6000/predicates.md index 28f4f5d98..8c384b380 100644 --- a/gcc-4.9/gcc/config/rs6000/predicates.md +++ b/gcc-4.9/gcc/config/rs6000/predicates.md @@ -171,6 +171,11 @@ (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) +;; Match op = 0..3. +(define_predicate "const_0_to_3_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) + ;; Match op = 2 or op = 3. (define_predicate "const_2_to_3_operand" (and (match_code "const_int") @@ -624,14 +629,14 @@ (match_test "offsettable_nonstrict_memref_p (op)"))) ;; Return 1 if the operand is suitable for load/store quad memory. -;; This predicate only checks for non-atomic loads/stores. +;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). (define_predicate "quad_memory_operand" (match_code "mem") { rtx addr, op0, op1; int ret; - if (!TARGET_QUAD_MEMORY) + if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) ret = 0; else if (!memory_operand (op, mode)) diff --git a/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def b/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def index 83351691f..8e15bdf16 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def @@ -570,6 +570,75 @@ MASK, /* MASK */ \ (ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \ CODE_FOR_nothing) /* ICODE */ + + +/* Decimal floating point builtins for instructions. */ +#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_DFP, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_DFP, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + +/* Miscellaneous builtins for instructions added in ISA 2.06. These + instructions don't require either the DFP or VSX options, just the basic ISA + 2.06 (popcntd) enablement since they operate on general purpose + registers. */ +#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_POPCNTD, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + + +/* Miscellaneous builtins for instructions added in ISA 2.07. These + instructions do require the ISA 2.07 vector support, but they aren't vector + instructions. */ +#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_P8_VECTOR, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_TERNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +/* Miscellaneous builtins. */ +#define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HARD_FLOAT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_" NAME, /* NAME */ \ + RS6000_BTM_HARD_FLOAT, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + #endif /* Insure 0 is not a legitimate index. */ @@ -1412,10 +1481,10 @@ BU_P8V_AV_2 (ORC_V4SF, "orc_v4sf", CONST, orcv4sf3) BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) /* 3 argument altivec instructions added in ISA 2.07. */ -BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) -BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) -BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) -BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) +BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) +BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) +BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) +BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) /* Vector comparison instructions added in ISA 2.07. */ BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) @@ -1474,6 +1543,64 @@ BU_P8V_OVERLOAD_3 (VADDEUQM, "vaddeuqm") BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq") BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm") + +/* 2 argument extended divide functions added in ISA 2.06. */ +BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) +BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si) +BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) +BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si) +BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di) +BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di) +BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) +BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di) + +/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */ +BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd) +BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td) + +/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */ +BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd) +BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td) +BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd) +BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td) +BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd) +BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td) +BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd) +BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td) +BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd) +BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td) + +/* 1 argument BCD functions added in ISA 2.06. */ +BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd) +BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd) + +/* 2 argument BCD functions added in ISA 2.06. */ +BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s) + +/* 3 argument BCD functions added in ISA 2.07. */ +BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd) +BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt) +BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq) +BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt) +BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered) +BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub) +BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt) +BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq) +BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt) +BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered) + +/* 2 argument pack/unpack 128-bit floating point types. */ +BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd) +BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd) + +BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf) +BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) +BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0) +BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1) + +BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) +BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) + /* 1 argument crypto functions. */ BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.c b/gcc-4.9/gcc/config/rs6000/rs6000.c index 494efc562..4f1a399a2 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.c +++ b/gcc-4.9/gcc/config/rs6000/rs6000.c @@ -2283,6 +2283,24 @@ rs6000_debug_reg_global (void) if (rs6000_float_gprs) fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true"); + fprintf (stderr, DEBUG_FMT_S, "fprs", + (TARGET_FPRS ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "single_float", + (TARGET_SINGLE_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "double_float", + (TARGET_DOUBLE_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "soft_float", + (TARGET_SOFT_FLOAT ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "e500_single", + (TARGET_E500_SINGLE ? "true" : "false")); + + fprintf (stderr, DEBUG_FMT_S, "e500_double", + (TARGET_E500_DOUBLE ? "true" : "false")); + if (TARGET_LINK_STACK) fprintf (stderr, DEBUG_FMT_S, "link_stack", "true"); @@ -3017,7 +3035,9 @@ rs6000_builtin_mask_calculate (void) | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) - | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)); + | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) + | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) + | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)); } /* Override command line options. Mostly we process the processor type and @@ -3374,6 +3394,13 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE; } + if (TARGET_DFP && !TARGET_HARD_FLOAT) + { + if (rs6000_isa_flags_explicit & OPTION_MASK_DFP) + error ("-mhard-dfp requires -mhard-float"); + rs6000_isa_flags &= ~OPTION_MASK_DFP; + } + /* The quad memory instructions only works in 64-bit mode. In 32-bit mode, silently turn off quad memory mode. */ if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64) @@ -12381,7 +12408,15 @@ rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) } } else if (icode == CODE_FOR_vsx_set_v2df - || icode == CODE_FOR_vsx_set_v2di) + || icode == CODE_FOR_vsx_set_v2di + || icode == CODE_FOR_bcdadd + || icode == CODE_FOR_bcdadd_lt + || icode == CODE_FOR_bcdadd_eq + || icode == CODE_FOR_bcdadd_gt + || icode == CODE_FOR_bcdsub + || icode == CODE_FOR_bcdsub_lt + || icode == CODE_FOR_bcdsub_eq + || icode == CODE_FOR_bcdsub_gt) { /* Only allow 1-bit unsigned literals. */ STRIP_NOPS (arg2); @@ -12392,6 +12427,44 @@ rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) return const0_rtx; } } + else if (icode == CODE_FOR_dfp_ddedpd_dd + || icode == CODE_FOR_dfp_ddedpd_td) + { + /* Only allow 2-bit unsigned literals where the value is 0 or 2. */ + STRIP_NOPS (arg0); + if (TREE_CODE (arg0) != INTEGER_CST + || TREE_INT_CST_LOW (arg2) & ~0x3) + { + error ("argument 1 must be 0 or 2"); + return const0_rtx; + } + } + else if (icode == CODE_FOR_dfp_denbcd_dd + || icode == CODE_FOR_dfp_denbcd_td) + { + /* Only allow 1-bit unsigned literals. */ + STRIP_NOPS (arg0); + if (TREE_CODE (arg0) != INTEGER_CST + || TREE_INT_CST_LOW (arg0) & ~0x1) + { + error ("argument 1 must be a 1-bit unsigned literal"); + return const0_rtx; + } + } + else if (icode == CODE_FOR_dfp_dscli_dd + || icode == CODE_FOR_dfp_dscli_td + || icode == CODE_FOR_dfp_dscri_dd + || icode == CODE_FOR_dfp_dscri_td) + { + /* Only allow 6-bit unsigned literals. */ + STRIP_NOPS (arg1); + if (TREE_CODE (arg1) != INTEGER_CST + || TREE_INT_CST_LOW (arg1) & ~0x3f) + { + error ("argument 2 must be a 6-bit unsigned literal"); + return const0_rtx; + } + } else if (icode == CODE_FOR_crypto_vshasigmaw || icode == CODE_FOR_crypto_vshasigmad) { @@ -13483,6 +13556,16 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode) error ("Builtin function %s requires the -mpaired option", name); else if ((fnmask & RS6000_BTM_SPE) != 0) error ("Builtin function %s requires the -mspe option", name); + else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) + == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) + error ("Builtin function %s requires the -mhard-dfp and" + "-mpower8-vector options", name); + else if ((fnmask & RS6000_BTM_DFP) != 0) + error ("Builtin function %s requires the -mhard-dfp option", name); + else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0) + error ("Builtin function %s requires the -mpower8-vector option", name); + else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0) + error ("Builtin function %s requires the -mhard-float option", name); else error ("Builtin function %s is not supported with the current options", name); @@ -13671,7 +13754,10 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return ret; } - gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT); + unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK; + gcc_assert (attr == RS6000_BTC_UNARY + || attr == RS6000_BTC_BINARY + || attr == RS6000_BTC_TERNARY); /* Handle simple unary operations. */ d = bdesc_1arg; @@ -13762,6 +13848,9 @@ rs6000_init_builtins (void) uintTI_type_internal_node = unsigned_intTI_type_node; float_type_internal_node = float_type_node; double_type_internal_node = double_type_node; + long_double_type_internal_node = long_double_type_node; + dfloat64_type_internal_node = dfloat64_type_node; + dfloat128_type_internal_node = dfloat128_type_node; void_type_internal_node = void_type_node; /* Initialize the modes for builtin_function_type, mapping a machine mode to @@ -13776,6 +13865,9 @@ rs6000_init_builtins (void) builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node; builtin_mode_to_type[SFmode][0] = float_type_node; builtin_mode_to_type[DFmode][0] = double_type_node; + builtin_mode_to_type[TFmode][0] = long_double_type_node; + builtin_mode_to_type[DDmode][0] = dfloat64_type_node; + builtin_mode_to_type[TDmode][0] = dfloat128_type_node; builtin_mode_to_type[V1TImode][0] = V1TI_type_node; builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node; builtin_mode_to_type[V2SImode][0] = V2SI_type_node; @@ -14868,6 +14960,8 @@ builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0, /* unsigned 1 argument functions. */ case CRYPTO_BUILTIN_VSBOX: case P8V_BUILTIN_VGBBD: + case MISC_BUILTIN_CDTBCD: + case MISC_BUILTIN_CBCDTD: h.uns_p[0] = 1; h.uns_p[1] = 1; break; @@ -14886,6 +14980,11 @@ builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0, case CRYPTO_BUILTIN_VPMSUMW: case CRYPTO_BUILTIN_VPMSUMD: case CRYPTO_BUILTIN_VPMSUM: + case MISC_BUILTIN_ADDG6S: + case MISC_BUILTIN_DIVWEU: + case MISC_BUILTIN_DIVWEUO: + case MISC_BUILTIN_DIVDEU: + case MISC_BUILTIN_DIVDEUO: h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; @@ -14947,9 +15046,18 @@ builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0, /* signed args, unsigned return. */ case VSX_BUILTIN_XVCVDPUXDS_UNS: case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI: + case MISC_BUILTIN_UNPACK_TD: + case MISC_BUILTIN_UNPACK_V1TI: h.uns_p[0] = 1; break; + /* unsigned arguments for 128-bit pack instructions. */ + case MISC_BUILTIN_PACK_TD: + case MISC_BUILTIN_PACK_V1TI: + h.uns_p[1] = 1; + h.uns_p[2] = 1; + break; + default: break; } @@ -31203,6 +31311,8 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, { "crypto", RS6000_BTM_CRYPTO, false, false }, { "htm", RS6000_BTM_HTM, false, false }, + { "hard-dfp", RS6000_BTM_DFP, false, false }, + { "hard-float", RS6000_BTM_HARD_FLOAT, false, false }, }; /* Option variables that we want to support inside attribute((target)) and diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.h b/gcc-4.9/gcc/config/rs6000/rs6000.h index 9ec3647fe..21330dc65 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.h +++ b/gcc-4.9/gcc/config/rs6000/rs6000.h @@ -624,7 +624,8 @@ extern int rs6000_vector_align[]; || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ - || TARGET_VSX))) + || TARGET_VSX \ + || TARGET_HARD_FLOAT))) /* E500 cores only support plain "sync", not lwsync. */ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ @@ -2516,6 +2517,8 @@ extern int frame_pointer_needed; #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ +#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ +#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ @@ -2527,7 +2530,9 @@ extern int frame_pointer_needed; | RS6000_BTM_FRSQRTES \ | RS6000_BTM_HTM \ | RS6000_BTM_POPCNTD \ - | RS6000_BTM_CELL) + | RS6000_BTM_CELL \ + | RS6000_BTM_DFP \ + | RS6000_BTM_HARD_FLOAT) /* Define builtin enum index. */ @@ -2622,6 +2627,9 @@ enum rs6000_builtin_type_index RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ RS6000_BTI_float, /* float_type_node */ RS6000_BTI_double, /* double_type_node */ + RS6000_BTI_long_double, /* long_double_type_node */ + RS6000_BTI_dfloat64, /* dfloat64_type_node */ + RS6000_BTI_dfloat128, /* dfloat128_type_node */ RS6000_BTI_void, /* void_type_node */ RS6000_BTI_MAX }; @@ -2673,6 +2681,9 @@ enum rs6000_builtin_type_index #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) +#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) +#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) +#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.md b/gcc-4.9/gcc/config/rs6000/rs6000.md index 64c9e7c10..e853bc4f9 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.md +++ b/gcc-4.9/gcc/config/rs6000/rs6000.md @@ -125,6 +125,16 @@ UNSPEC_P8V_MTVSRD UNSPEC_P8V_XXPERMDI UNSPEC_P8V_RELOAD_FROM_VSX + UNSPEC_ADDG6S + UNSPEC_CDTBCD + UNSPEC_CBCDTD + UNSPEC_DIVE + UNSPEC_DIVEO + UNSPEC_DIVEU + UNSPEC_DIVEUO + UNSPEC_UNPACK_128BIT + UNSPEC_PACK_128BIT + UNSPEC_LSQ ]) ;; @@ -481,6 +491,10 @@ (V2DF "X,X,X,X,X") (V1TI "X,X,X,X,X")]) +;; Mode attribute to give the correct type for integer divides +(define_mode_attr idiv_ldiv [(SI "idiv") + (DI "ldiv")]) + ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. @@ -2755,10 +2769,7 @@ (match_operand:GPR 2 "gpc_reg_operand" "r")))] "" "divu %0,%1,%2" - [(set (attr "type") - (cond [(match_operand:SI 0 "" "") - (const_string "idiv")] - (const_string "ldiv")))]) + [(set_attr "type" "")]) ;; For powers of two we can do srai/aze for divide and then adjust for @@ -2782,10 +2793,7 @@ (match_operand:GPR 2 "gpc_reg_operand" "r")))] "" "div %0,%1,%2" - [(set (attr "type") - (cond [(match_operand:SI 0 "" "") - (const_string "idiv")] - (const_string "ldiv")))]) + [(set_attr "type" "")]) (define_expand "mod3" [(use (match_operand:GPR 0 "gpc_reg_operand" "")) @@ -6534,6 +6542,49 @@ [(set_attr "length" "8") (set_attr "type" "fpload")]) +;; Define the TImode operations that can be done in a small number +;; of instructions. The & constraints are to prevent the register +;; allocator from allocating registers that overlap with the inputs +;; (for example, having an input in 7,8 and an output in 6,7). We +;; also allow for the output being the same as one of the inputs. + +(define_insn "addti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") + (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] + "TARGET_64BIT" +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[2])) != CONST_INT + ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" + : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; + else + return (GET_CODE (operands[2])) != CONST_INT + ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" + : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + +(define_insn "subti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r") + (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I") + (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))] + "TARGET_64BIT" +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[1]) != CONST_INT) + ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" + : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; + else + return (GET_CODE (operands[1]) != CONST_INT) + ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" + : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + + ;; Define the DImode operations that can be done in a small number ;; of instructions. The & constraints are to prevent the register ;; allocator from allocating registers that overlap with the inputs @@ -9395,7 +9446,8 @@ (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] "! TARGET_POWERPC64 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) - || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) + || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE + || (mode == DDmode && TARGET_E500_DOUBLE)) && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" "#" @@ -15690,6 +15742,191 @@ DONE; }) + +;; Miscellaneous ISA 2.06 (power7) instructions +(define_insn "addg6s" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_ADDG6S))] + "TARGET_POPCNTD" + "addg6s %0,%1,%2" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + +(define_insn "cdtbcd" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CDTBCD))] + "TARGET_POPCNTD" + "cdtbcd %0,%1" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + +(define_insn "cbcdtd" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CBCDTD))] + "TARGET_POPCNTD" + "cbcdtd %0,%1" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + +(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE + UNSPEC_DIVEO + UNSPEC_DIVEU + UNSPEC_DIVEUO]) + +(define_int_attr div_extend [(UNSPEC_DIVE "e") + (UNSPEC_DIVEO "eo") + (UNSPEC_DIVEU "eu") + (UNSPEC_DIVEUO "euo")]) + +(define_insn "div_" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") + (match_operand:GPR 2 "register_operand" "r")] + UNSPEC_DIV_EXTEND))] + "TARGET_POPCNTD" + "div %0,%1,%2" + [(set_attr "type" "")]) + + +;; Pack/unpack 128-bit floating point types that take 2 scalar registers + +; Type of the 64-bit part when packing/unpacking 128-bit floating point types +(define_mode_attr FP128_64 [(TF "DF") (TD "DI")]) + +(define_expand "unpack" + [(set (match_operand: 0 "nonimmediate_operand" "") + (unspec: + [(match_operand:FMOVE128 1 "register_operand" "") + (match_operand:QI 2 "const_0_to_1_operand" "")] + UNSPEC_UNPACK_128BIT))] + "" + "") + +;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0 +;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these +;; builtins here. + +(define_expand "unpacktf_0" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (unspec:DF [(match_operand:TF 1 "register_operand" "") + (const_int 0)] + UNSPEC_UNPACK_128BIT))] + "" + "") + +(define_expand "unpacktf_1" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (unspec:DF [(match_operand:TF 1 "register_operand" "") + (const_int 1)] + UNSPEC_UNPACK_128BIT))] + "" + "") + +(define_insn_and_split "unpack_dm" + [(set (match_operand: 0 "nonimmediate_operand" "=d,m,d,r,m") + (unspec: + [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") + (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] + UNSPEC_UNPACK_128BIT))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); + + if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) + { + emit_note (NOTE_INSN_DELETED); + DONE; + } + + operands[3] = gen_rtx_REG (mode, fp_regno); +} + [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store") + (set_attr "length" "4")]) + +(define_insn_and_split "unpack_nodm" + [(set (match_operand: 0 "nonimmediate_operand" "=d,m") + (unspec: + [(match_operand:FMOVE128 1 "register_operand" "d,d") + (match_operand:QI 2 "const_0_to_1_operand" "i,i")] + UNSPEC_UNPACK_128BIT))] + "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); + + if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) + { + emit_note (NOTE_INSN_DELETED); + DONE; + } + + operands[3] = gen_rtx_REG (mode, fp_regno); +} + [(set_attr "type" "fp,fpstore") + (set_attr "length" "4")]) + +(define_insn_and_split "pack" + [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d") + (unspec:FMOVE128 + [(match_operand: 1 "register_operand" "0,d") + (match_operand: 2 "register_operand" "d,d")] + UNSPEC_PACK_128BIT))] + "" + "@ + fmr %L0,%2 + #" + "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 4) (match_dup 2))] +{ + unsigned dest_hi = REGNO (operands[0]); + unsigned dest_lo = dest_hi + 1; + + gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo)); + gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo)); + + operands[3] = gen_rtx_REG (mode, dest_hi); + operands[4] = gen_rtx_REG (mode, dest_lo); +} + [(set_attr "type" "fp,fp") + (set_attr "length" "4,8")]) + +(define_insn "unpackv1ti" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa") + (match_operand:QI 2 "const_0_to_1_operand" "O,i")] + UNSPEC_UNPACK_128BIT))] + "TARGET_VSX" +{ + if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0) + return ASM_COMMENT_START " xxpermdi to same register"; + + operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3); + return "xxpermdi %x0,%x1,%x1,%3"; +} + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + +(define_insn "packv1ti" + [(set (match_operand:V1TI 0 "register_operand" "=wa") + (unspec:V1TI + [(match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")] + UNSPEC_PACK_128BIT))] + "TARGET_VSX" + "xxpermdi %x0,%x1,%x2,0" + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + (include "sync.md") diff --git a/gcc-4.9/gcc/config/rs6000/sync.md b/gcc-4.9/gcc/config/rs6000/sync.md index 7db439074..63152ed04 100644 --- a/gcc-4.9/gcc/config/rs6000/sync.md +++ b/gcc-4.9/gcc/config/rs6000/sync.md @@ -107,10 +107,17 @@ "isync" [(set_attr "type" "isync")]) +;; Types that we should provide atomic instructions for. +(define_mode_iterator AINT [QI + HI + SI + (DI "TARGET_POWERPC64") + (TI "TARGET_SYNC_TI")]) + ;; The control dependency used for load dependency described ;; in B.2.3 of the Power ISA 2.06B. (define_insn "loadsync_" - [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")] + [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")] UNSPECV_ISYNC) (clobber (match_scratch:CC 1 "=y"))] "" @@ -118,18 +125,56 @@ [(set_attr "type" "isync") (set_attr "length" "12")]) +(define_insn "load_quadpti" + [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") + (unspec:PTI + [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))] + "TARGET_SYNC_TI + && !reg_mentioned_p (operands[0], operands[1])" + "lq %0,%1" + [(set_attr "type" "load") + (set_attr "length" "4")]) + (define_expand "atomic_load" - [(set (match_operand:INT1 0 "register_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "")) ;; memory + [(set (match_operand:AINT 0 "register_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "")) ;; memory (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { + if (mode == TImode && !TARGET_SYNC_TI) + FAIL; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); if (model == MEMMODEL_SEQ_CST) emit_insn (gen_hwsync ()); - emit_move_insn (operands[0], operands[1]); + if (mode != TImode) + emit_move_insn (operands[0], operands[1]); + else + { + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti_reg = gen_reg_rtx (PTImode); + + // Can't have indexed address for 'lq' + if (indexed_address (XEXP (op1, 0), TImode)) + { + rtx old_addr = XEXP (op1, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[1] = op1 = replace_equiv_address (op1, new_addr); + } + + emit_insn (gen_load_quadpti (pti_reg, op1)); + + if (WORDS_BIG_ENDIAN) + emit_move_insn (op0, gen_lowpart (TImode, pti_reg)); + else + { + emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg)); + emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg)); + } + } switch (model) { @@ -146,12 +191,24 @@ DONE; }) +(define_insn "store_quadpti" + [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ") + (unspec:PTI + [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] + "TARGET_SYNC_TI" + "stq %1,%0" + [(set_attr "type" "store") + (set_attr "length" "4")]) + (define_expand "atomic_store" - [(set (match_operand:INT1 0 "memory_operand" "") ;; memory - (match_operand:INT1 1 "register_operand" "")) ;; input + [(set (match_operand:AINT 0 "memory_operand" "") ;; memory + (match_operand:AINT 1 "register_operand" "")) ;; input (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { + if (mode == TImode && !TARGET_SYNC_TI) + FAIL; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); switch (model) { @@ -166,7 +223,33 @@ default: gcc_unreachable (); } - emit_move_insn (operands[0], operands[1]); + if (mode != TImode) + emit_move_insn (operands[0], operands[1]); + else + { + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti_reg = gen_reg_rtx (PTImode); + + // Can't have indexed address for 'stq' + if (indexed_address (XEXP (op0, 0), TImode)) + { + rtx old_addr = XEXP (op0, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[0] = op0 = replace_equiv_address (op0, new_addr); + } + + if (WORDS_BIG_ENDIAN) + emit_move_insn (pti_reg, gen_lowpart (PTImode, op1)); + else + { + emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1)); + emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1)); + } + + emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg)); + } + DONE; }) @@ -180,14 +263,6 @@ SI (DI "TARGET_POWERPC64")]) -;; Types that we should provide atomic instructions for. - -(define_mode_iterator AINT [QI - HI - SI - (DI "TARGET_POWERPC64") - (TI "TARGET_SYNC_TI")]) - (define_insn "load_locked" [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r") (unspec_volatile:ATOMIC diff --git a/gcc-4.9/gcc/config/rs6000/vsx.md b/gcc-4.9/gcc/config/rs6000/vsx.md index d83cdc3df..23d85ab06 100644 --- a/gcc-4.9/gcc/config/rs6000/vsx.md +++ b/gcc-4.9/gcc/config/rs6000/vsx.md @@ -1891,7 +1891,12 @@ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (mode)" - "xxmrghw %x0,%x1,%x2" +{ + if (BYTES_BIG_ENDIAN) + return "xxmrghw %x0,%x1,%x2"; + else + return "xxmrglw %x0,%x2,%x1"; +} [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_" @@ -1903,7 +1908,12 @@ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (mode)" - "xxmrglw %x0,%x1,%x2" +{ + if (BYTES_BIG_ENDIAN) + return "xxmrglw %x0,%x1,%x2"; + else + return "xxmrghw %x0,%x2,%x1"; +} [(set_attr "type" "vecperm")]) ;; Shift left double by word immediate diff --git a/gcc-4.9/gcc/config/sh/sh.c b/gcc-4.9/gcc/config/sh/sh.c index 6d909c79e..12724a20d 100644 --- a/gcc-4.9/gcc/config/sh/sh.c +++ b/gcc-4.9/gcc/config/sh/sh.c @@ -19,6 +19,10 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ +#include +#include +#include + #include "config.h" #include "system.h" #include "coretypes.h" @@ -70,10 +74,6 @@ along with GCC; see the file COPYING3. If not see #include "pass_manager.h" #include "context.h" -#include -#include -#include - int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; /* These are some macros to abstract register modes. */ diff --git a/gcc-4.9/gcc/config/sparc/sparc-protos.h b/gcc-4.9/gcc/config/sparc/sparc-protos.h index 1d63e4640..ee2091bb8 100644 --- a/gcc-4.9/gcc/config/sparc/sparc-protos.h +++ b/gcc-4.9/gcc/config/sparc/sparc-protos.h @@ -69,7 +69,6 @@ extern bool sparc_expand_move (enum machine_mode, rtx *); extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx); extern int sparc_splitdi_legitimate (rtx, rtx); extern int sparc_split_regreg_legitimate (rtx, rtx); -extern int sparc_absnegfloat_split_legitimate (rtx, rtx); extern const char *output_ubranch (rtx, rtx); extern const char *output_cbranch (rtx, rtx, int, int, int, rtx); extern const char *output_return (rtx); diff --git a/gcc-4.9/gcc/config/sparc/sparc.c b/gcc-4.9/gcc/config/sparc/sparc.c index f52b9761a..5b00cca47 100644 --- a/gcc-4.9/gcc/config/sparc/sparc.c +++ b/gcc-4.9/gcc/config/sparc/sparc.c @@ -8539,22 +8539,6 @@ sparc_split_regreg_legitimate (rtx reg1, rtx reg2) return 0; } -/* Return 1 if x and y are some kind of REG and they refer to - different hard registers. This test is guaranteed to be - run after reload. */ - -int -sparc_absnegfloat_split_legitimate (rtx x, rtx y) -{ - if (GET_CODE (x) != REG) - return 0; - if (GET_CODE (y) != REG) - return 0; - if (REGNO (x) == REGNO (y)) - return 0; - return 1; -} - /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. This makes them candidates for using ldd and std insns. diff --git a/gcc-4.9/gcc/config/sparc/sparc.md b/gcc-4.9/gcc/config/sparc/sparc.md index 8b6c647fc..76c331597 100644 --- a/gcc-4.9/gcc/config/sparc/sparc.md +++ b/gcc-4.9/gcc/config/sparc/sparc.md @@ -424,6 +424,10 @@ (define_attr "fptype" "single,double" (const_string "single")) +;; FP precision specific to the UT699. +(define_attr "fptype_ut699" "none,single" + (const_string "none")) + ;; UltraSPARC-III integer load type. (define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle")) @@ -464,7 +468,8 @@ (const_string "false") (and (eq_attr "fix_ut699" "true") (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts") - (eq_attr "fptype" "single"))) + (ior (eq_attr "fptype" "single") + (eq_attr "fptype_ut699" "single")))) (const_string "false") (eq_attr "length" "1") (const_string "true") @@ -3455,7 +3460,8 @@ "TARGET_FPU" "fdtos\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "fptype_ut699" "single")]) (define_expand "trunctfsf2" [(set (match_operand:SF 0 "register_operand" "") @@ -3496,7 +3502,7 @@ "TARGET_FPU" "fitos\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "single")]) (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=e") @@ -3583,7 +3589,7 @@ "TARGET_FPU" "fstoi\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "single")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=f") @@ -3591,7 +3597,8 @@ "TARGET_FPU" "fdtoi\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "fptype_ut699" "single")]) (define_expand "fix_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "") @@ -5554,53 +5561,52 @@ [(set_attr "type" "fpdivs")]) (define_expand "negtf2" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] + [(set (match_operand:TF 0 "register_operand" "") + (neg:TF (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU" "") -(define_insn_and_split "*negtf2_notv9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU - && ! TARGET_V9" - "@ - fnegs\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); - operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_insn_and_split "*negtf2_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU && TARGET_V9" - "@ - fnegd\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:DF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double")]) +(define_insn "*negtf2_hq" + [(set (match_operand:TF 0 "register_operand" "=e") + (neg:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fnegq\t%1, %0" + [(set_attr "type" "fpmove")]) + +(define_insn_and_split "*negtf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (neg:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_HARD_QUAD" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_df_reg (set_dest, 0); + dest2 = gen_df_reg (set_dest, 1); + src1 = gen_df_reg (set_src, 0); + src2 = gen_df_reg (set_src, 1); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_negdf2 (dest1, src1)); + } + else + { + emit_insn (gen_negdf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_expand "negdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -5609,22 +5615,39 @@ "") (define_insn_and_split "*negdf2_notv9" - [(set (match_operand:DF 0 "register_operand" "=e,e") - (neg:DF (match_operand:DF 1 "register_operand" "0,e")))] - "TARGET_FPU && ! TARGET_V9" - "@ - fnegs\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) + [(set (match_operand:DF 0 "register_operand" "=e") + (neg:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_V9" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_negsf2 (dest1, src1)); + } + else + { + emit_insn (gen_negsf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_insn "*negdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5647,56 +5670,47 @@ "TARGET_FPU" "") -(define_insn_and_split "*abstf2_notv9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU && ! TARGET_V9" - "@ - fabss\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); - operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_insn "*abstf2_hq_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD" - "@ - fabsd\t%0, %0 - fabsq\t%1, %0" - [(set_attr "type" "fpmove") - (set_attr "fptype" "double,*")]) +(define_insn "*abstf2_hq" + [(set (match_operand:TF 0 "register_operand" "=e") + (abs:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fabsq\t%1, %0" + [(set_attr "type" "fpmove")]) -(define_insn_and_split "*abstf2_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD" - "@ - fabsd\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:DF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double,*")]) +(define_insn_and_split "*abstf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (abs:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_HARD_QUAD" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_df_reg (set_dest, 0); + dest2 = gen_df_reg (set_dest, 1); + src1 = gen_df_reg (set_src, 0); + src2 = gen_df_reg (set_src, 1); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_absdf2 (dest1, src1)); + } + else + { + emit_insn (gen_absdf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_expand "absdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -5705,22 +5719,39 @@ "") (define_insn_and_split "*absdf2_notv9" - [(set (match_operand:DF 0 "register_operand" "=e,e") - (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] - "TARGET_FPU && ! TARGET_V9" - "@ - fabss\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) + [(set (match_operand:DF 0 "register_operand" "=e") + (abs:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_V9" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_abssf2 (dest1, src1)); + } + else + { + emit_insn (gen_abssf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_insn "*absdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5795,19 +5826,6 @@ } [(set_attr "type" "shift")]) -(define_insn "*ashlsi3_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI"))))] - "TARGET_ARCH64" -{ - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "sll\t%1, %2, %0"; -} - [(set_attr "type" "shift")]) - (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") diff --git a/gcc-4.9/gcc/config/sparc/sparc.opt b/gcc-4.9/gcc/config/sparc/sparc.opt index c02aec59f..64e40955a 100644 --- a/gcc-4.9/gcc/config/sparc/sparc.opt +++ b/gcc-4.9/gcc/config/sparc/sparc.opt @@ -113,6 +113,10 @@ mrelax Target Optimize tail call instructions in assembler and linker +muser-mode +Target Report Mask(USER_MODE) +Do not generate code that can only run in supervisor mode + mcpu= Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7) Use features of and schedule code for given CPU diff --git a/gcc-4.9/gcc/config/sparc/sync.md b/gcc-4.9/gcc/config/sparc/sync.md index fd5691f73..e6e237f25 100644 --- a/gcc-4.9/gcc/config/sparc/sync.md +++ b/gcc-4.9/gcc/config/sparc/sync.md @@ -200,10 +200,27 @@ [(match_operand:I48MODE 2 "register_operand" "r") (match_operand:I48MODE 3 "register_operand" "0")] UNSPECV_CAS))] - "(TARGET_V9 || TARGET_LEON3) && (mode != DImode || TARGET_ARCH64)" + "TARGET_V9 && (mode != DImode || TARGET_ARCH64)" "cas\t%1, %2, %0" [(set_attr "type" "multi")]) +(define_insn "*atomic_compare_and_swap_leon3_1" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "mem_noofs_operand" "+w")) + (set (match_dup 1) + (unspec_volatile:SI + [(match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPECV_CAS))] + "TARGET_LEON3" +{ + if (TARGET_USER_MODE) + return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ + else + return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ +} + [(set_attr "type" "multi")]) + (define_insn "*atomic_compare_and_swapdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=h") (match_operand:DI 1 "mem_noofs_operand" "+w")) diff --git a/gcc-4.9/gcc/configure b/gcc-4.9/gcc/configure index 7b07b1b53..5408d8fbe 100755 --- a/gcc-4.9/gcc/configure +++ b/gcc-4.9/gcc/configure @@ -24503,7 +24503,7 @@ else .align 4 smac %g2, %g3, %g1 umac %g2, %g3, %g1 - cas [%g2], %g3, %g1' > conftest.s + casa [%g2] 0xb, %g3, %g1' > conftest.s if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5' { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 (eval $ac_try) 2>&5 diff --git a/gcc-4.9/gcc/configure.ac b/gcc-4.9/gcc/configure.ac index c7a593f52..011ec822e 100644 --- a/gcc-4.9/gcc/configure.ac +++ b/gcc-4.9/gcc/configure.ac @@ -3727,7 +3727,7 @@ foo: .align 4 smac %g2, %g3, %g1 umac %g2, %g3, %g1 - cas [[%g2]], %g3, %g1],, + casa [[%g2]] 0xb, %g3, %g1],, [AC_DEFINE(HAVE_AS_LEON, 1, [Define if your assembler supports LEON instructions.])]) ;; diff --git a/gcc-4.9/gcc/cp/ChangeLog b/gcc-4.9/gcc/cp/ChangeLog index f95944b9b..f9cf11884 100644 --- a/gcc-4.9/gcc/cp/ChangeLog +++ b/gcc-4.9/gcc/cp/ChangeLog @@ -1,3 +1,54 @@ +2014-05-13 Jason Merrill + + PR c++/61151 + * lambda.c (is_this): Allow capture proxies too. + + DR 5 + PR c++/60019 + * call.c (build_user_type_conversion_1): The copy-init temporary + is cv-unqualified. + +2014-05-07 Paolo Carlini + + PR c++/61083 + * pt.c (convert_nontype_argument): Protect all the error calls + with complain & tf_error. + +2014-05-06 Paolo Carlini + + PR c++/60999 + * pt.c (maybe_begin_member_template_processing): Use + uses_template_parms. + +2014-05-02 Jason Merrill + + PR c++/60992 + * lambda.c (lambda_capture_field_type): Wrap anything dependent + other than 'this' or a VLA. + (is_this): New. + * pt.c (tsubst_copy) [VAR_DECL]: Also build a new VAR_DECL if + the operand was static or constant. + +2014-04-30 Jason Merrill + + PR c++/60980 + * init.c (build_value_init): Don't try to call an array constructor. + + PR c++/60951 + * typeck2.c (massage_init_elt): Use maybe_constant_init. + +2014-04-24 Jakub Jelinek + + * parser.c (cp_parser_omp_atomic): Allow seq_cst before + atomic-clause, allow comma in between atomic-clause and + seq_cst. + +2014-04-22 Jakub Jelinek + + PR c/59073 + * parser.c (cp_parser_omp_parallel): If cp_parser_omp_for + fails, don't set OM_PARALLEL_COMBINED and return NULL. + 2014-04-22 Release Manager * GCC 4.9.0 released. diff --git a/gcc-4.9/gcc/cp/call.c b/gcc-4.9/gcc/cp/call.c index 98469e9e4..57e08cb8e 100644 --- a/gcc-4.9/gcc/cp/call.c +++ b/gcc-4.9/gcc/cp/call.c @@ -3677,11 +3677,20 @@ build_user_type_conversion_1 (tree totype, tree expr, int flags, return cand; } + tree convtype; + if (!DECL_CONSTRUCTOR_P (cand->fn)) + convtype = non_reference (TREE_TYPE (TREE_TYPE (cand->fn))); + else if (cand->second_conv->kind == ck_rvalue) + /* DR 5: [in the first step of copy-initialization]...if the function + is a constructor, the call initializes a temporary of the + cv-unqualified version of the destination type. */ + convtype = cv_unqualified (totype); + else + convtype = totype; /* Build the user conversion sequence. */ conv = build_conv (ck_user, - (DECL_CONSTRUCTOR_P (cand->fn) - ? totype : non_reference (TREE_TYPE (TREE_TYPE (cand->fn)))), + convtype, build_identity_conv (TREE_TYPE (expr), expr)); conv->cand = cand; if (cand->viable == -1) diff --git a/gcc-4.9/gcc/cp/init.c b/gcc-4.9/gcc/cp/init.c index 1a1f6c0fe..4373963a2 100644 --- a/gcc-4.9/gcc/cp/init.c +++ b/gcc-4.9/gcc/cp/init.c @@ -339,7 +339,8 @@ build_value_init (tree type, tsubst_flags_t complain) gcc_assert (!processing_template_decl || (SCALAR_TYPE_P (type) || TREE_CODE (type) == ARRAY_TYPE)); - if (type_build_ctor_call (type)) + if (CLASS_TYPE_P (type) + && type_build_ctor_call (type)) { tree ctor = build_aggr_init_expr (type, diff --git a/gcc-4.9/gcc/cp/lambda.c b/gcc-4.9/gcc/cp/lambda.c index 0b8b46a81..7bd0de15f 100644 --- a/gcc-4.9/gcc/cp/lambda.c +++ b/gcc-4.9/gcc/cp/lambda.c @@ -201,6 +201,14 @@ lambda_function (tree lambda) return lambda; } +static inline bool +is_this (tree t) +{ + return ((TREE_CODE (t) == PARM_DECL + || TREE_CODE (t) == VAR_DECL) + && DECL_NAME (t) == this_identifier); +} + /* Returns the type to use for the FIELD_DECL corresponding to the capture of EXPR. The caller should add REFERENCE_TYPE for capture by reference. */ @@ -216,8 +224,9 @@ lambda_capture_field_type (tree expr, bool explicit_init_p) } else type = non_reference (unlowered_expr_type (expr)); - if (!type || WILDCARD_TYPE_P (type) || type_uses_auto (type) - || DECL_PACK_P (expr)) + if (type_dependent_expression_p (expr) + && !is_this (tree_strip_nop_conversions (expr)) + && !array_of_runtime_bound_p (type)) { type = cxx_make_type (DECLTYPE_TYPE); DECLTYPE_TYPE_EXPR (type) = expr; diff --git a/gcc-4.9/gcc/cp/parser.c b/gcc-4.9/gcc/cp/parser.c index f386eed27..aa00a7b68 100644 --- a/gcc-4.9/gcc/cp/parser.c +++ b/gcc-4.9/gcc/cp/parser.c @@ -28525,6 +28525,20 @@ cp_parser_omp_atomic (cp_parser *parser, cp_token *pragma_tok) bool structured_block = false; bool seq_cst = false; + if (cp_lexer_next_token_is (parser->lexer, CPP_NAME)) + { + tree id = cp_lexer_peek_token (parser->lexer)->u.value; + const char *p = IDENTIFIER_POINTER (id); + + if (!strcmp (p, "seq_cst")) + { + seq_cst = true; + cp_lexer_consume_token (parser->lexer); + if (cp_lexer_next_token_is (parser->lexer, CPP_COMMA) + && cp_lexer_peek_nth_token (parser->lexer, 2)->type == CPP_NAME) + cp_lexer_consume_token (parser->lexer); + } + } if (cp_lexer_next_token_is (parser->lexer, CPP_NAME)) { tree id = cp_lexer_peek_token (parser->lexer)->u.value; @@ -28543,16 +28557,22 @@ cp_parser_omp_atomic (cp_parser *parser, cp_token *pragma_tok) if (p) cp_lexer_consume_token (parser->lexer); } - - if (cp_lexer_next_token_is (parser->lexer, CPP_NAME)) + if (!seq_cst) { - tree id = cp_lexer_peek_token (parser->lexer)->u.value; - const char *p = IDENTIFIER_POINTER (id); + if (cp_lexer_next_token_is (parser->lexer, CPP_COMMA) + && cp_lexer_peek_nth_token (parser->lexer, 2)->type == CPP_NAME) + cp_lexer_consume_token (parser->lexer); - if (!strcmp (p, "seq_cst")) + if (cp_lexer_next_token_is (parser->lexer, CPP_NAME)) { - seq_cst = true; - cp_lexer_consume_token (parser->lexer); + tree id = cp_lexer_peek_token (parser->lexer)->u.value; + const char *p = IDENTIFIER_POINTER (id); + + if (!strcmp (p, "seq_cst")) + { + seq_cst = true; + cp_lexer_consume_token (parser->lexer); + } } } cp_parser_require_pragma_eol (parser, pragma_tok); @@ -29825,10 +29845,12 @@ cp_parser_omp_parallel (cp_parser *parser, cp_token *pragma_tok, return cp_parser_omp_for (parser, pragma_tok, p_name, mask, cclauses); block = begin_omp_parallel (); save = cp_parser_begin_omp_structured_block (parser); - cp_parser_omp_for (parser, pragma_tok, p_name, mask, cclauses); + tree ret = cp_parser_omp_for (parser, pragma_tok, p_name, mask, cclauses); cp_parser_end_omp_structured_block (parser, save); stmt = finish_omp_parallel (cclauses[C_OMP_CLAUSE_SPLIT_PARALLEL], block); + if (ret == NULL_TREE) + return ret; OMP_PARALLEL_COMBINED (stmt) = 1; return stmt; } diff --git a/gcc-4.9/gcc/cp/pt.c b/gcc-4.9/gcc/cp/pt.c index 318c32507..3951997b0 100644 --- a/gcc-4.9/gcc/cp/pt.c +++ b/gcc-4.9/gcc/cp/pt.c @@ -462,9 +462,13 @@ maybe_begin_member_template_processing (tree decl) bool nsdmi = TREE_CODE (decl) == FIELD_DECL; if (nsdmi) - decl = (CLASSTYPE_TEMPLATE_INFO (DECL_CONTEXT (decl)) - ? CLASSTYPE_TI_TEMPLATE (DECL_CONTEXT (decl)) - : NULL_TREE); + { + tree ctx = DECL_CONTEXT (decl); + decl = (CLASSTYPE_TEMPLATE_INFO (ctx) + /* Disregard full specializations (c++/60999). */ + && uses_template_parms (ctx) + ? CLASSTYPE_TI_TEMPLATE (ctx) : NULL_TREE); + } if (inline_needs_template_parms (decl, nsdmi)) { @@ -5817,17 +5821,18 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) { if (VAR_P (expr)) { - error ("%qD is not a valid template argument " - "because %qD is a variable, not the address of " - "a variable", - expr, expr); + if (complain & tf_error) + error ("%qD is not a valid template argument " + "because %qD is a variable, not the address of " + "a variable", expr, expr); return NULL_TREE; } if (POINTER_TYPE_P (expr_type)) { - error ("%qE is not a valid template argument for %qT " - "because it is not the address of a variable", - expr, type); + if (complain & tf_error) + error ("%qE is not a valid template argument for %qT " + "because it is not the address of a variable", + expr, type); return NULL_TREE; } /* Other values, like integer constants, might be valid @@ -5842,23 +5847,24 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) ? TREE_OPERAND (expr, 0) : expr); if (!VAR_P (decl)) { - error ("%qE is not a valid template argument of type %qT " - "because %qE is not a variable", - expr, type, decl); + if (complain & tf_error) + error ("%qE is not a valid template argument of type %qT " + "because %qE is not a variable", expr, type, decl); return NULL_TREE; } else if (cxx_dialect < cxx11 && !DECL_EXTERNAL_LINKAGE_P (decl)) { - error ("%qE is not a valid template argument of type %qT " - "because %qD does not have external linkage", - expr, type, decl); + if (complain & tf_error) + error ("%qE is not a valid template argument of type %qT " + "because %qD does not have external linkage", + expr, type, decl); return NULL_TREE; } else if (cxx_dialect >= cxx11 && decl_linkage (decl) == lk_none) { - error ("%qE is not a valid template argument of type %qT " - "because %qD has no linkage", - expr, type, decl); + if (complain & tf_error) + error ("%qE is not a valid template argument of type %qT " + "because %qD has no linkage", expr, type, decl); return NULL_TREE; } } @@ -5886,15 +5892,17 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) if (!at_least_as_qualified_p (TREE_TYPE (type), expr_type)) { - error ("%qE is not a valid template argument for type %qT " - "because of conflicts in cv-qualification", expr, type); + if (complain & tf_error) + error ("%qE is not a valid template argument for type %qT " + "because of conflicts in cv-qualification", expr, type); return NULL_TREE; } if (!real_lvalue_p (expr)) { - error ("%qE is not a valid template argument for type %qT " - "because it is not an lvalue", expr, type); + if (complain & tf_error) + error ("%qE is not a valid template argument for type %qT " + "because it is not an lvalue", expr, type); return NULL_TREE; } @@ -5910,26 +5918,29 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) expr = TREE_OPERAND (expr, 0); if (DECL_P (expr)) { - error ("%q#D is not a valid template argument for type %qT " - "because a reference variable does not have a constant " - "address", expr, type); + if (complain & tf_error) + error ("%q#D is not a valid template argument for type %qT " + "because a reference variable does not have a constant " + "address", expr, type); return NULL_TREE; } } if (!DECL_P (expr)) { - error ("%qE is not a valid template argument for type %qT " - "because it is not an object with external linkage", - expr, type); + if (complain & tf_error) + error ("%qE is not a valid template argument for type %qT " + "because it is not an object with external linkage", + expr, type); return NULL_TREE; } if (!DECL_EXTERNAL_LINKAGE_P (expr)) { - error ("%qE is not a valid template argument for type %qT " - "because object %qD has not external linkage", - expr, type, expr); + if (complain & tf_error) + error ("%qE is not a valid template argument for type %qT " + "because object %qD has not external linkage", + expr, type, expr); return NULL_TREE; } @@ -5971,9 +5982,13 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) { if (TREE_CODE (expr) == ADDR_EXPR) { - error ("%qE is not a valid template argument for type %qT " - "because it is a pointer", expr, type); - inform (input_location, "try using %qE instead", TREE_OPERAND (expr, 0)); + if (complain & tf_error) + { + error ("%qE is not a valid template argument for type %qT " + "because it is a pointer", expr, type); + inform (input_location, "try using %qE instead", + TREE_OPERAND (expr, 0)); + } return NULL_TREE; } @@ -6011,13 +6026,16 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) provide a superior diagnostic. */ if (!same_type_p (TREE_TYPE (expr), type)) { - error ("%qE is not a valid template argument for type %qT " - "because it is of type %qT", expr, type, - TREE_TYPE (expr)); - /* If we are just one standard conversion off, explain. */ - if (can_convert_standard (type, TREE_TYPE (expr), complain)) - inform (input_location, - "standard conversions are not allowed in this context"); + if (complain & tf_error) + { + error ("%qE is not a valid template argument for type %qT " + "because it is of type %qT", expr, type, + TREE_TYPE (expr)); + /* If we are just one standard conversion off, explain. */ + if (can_convert_standard (type, TREE_TYPE (expr), complain)) + inform (input_location, + "standard conversions are not allowed in this context"); + } return NULL_TREE; } } @@ -6040,8 +6058,9 @@ convert_nontype_argument (tree type, tree expr, tsubst_flags_t complain) { if (expr != nullptr_node) { - error ("%qE is not a valid template argument for type %qT " - "because it is of type %qT", expr, type, TREE_TYPE (expr)); + if (complain & tf_error) + error ("%qE is not a valid template argument for type %qT " + "because it is of type %qT", expr, type, TREE_TYPE (expr)); return NULL_TREE; } return expr; @@ -12638,13 +12657,17 @@ tsubst_copy (tree t, tree args, tsubst_flags_t complain, tree in_decl) } else { - /* This can happen for a variable used in a late-specified - return type of a local lambda. Just make a dummy decl - since it's only used for its type. */ - if (cp_unevaluated_operand) - return tsubst_decl (t, args, complain); - gcc_assert (errorcount || sorrycount); - return error_mark_node; + /* This can happen for a variable used in a + late-specified return type of a local lambda, or for a + local static or constant. Building a new VAR_DECL + should be OK in all those cases. */ + r = tsubst_decl (t, args, complain); + if (decl_constant_var_p (r)) + /* A use of a local constant must decay to its value. */ + return integral_constant_value (r); + gcc_assert (cp_unevaluated_operand || TREE_STATIC (r) + || errorcount || sorrycount); + return r; } } } diff --git a/gcc-4.9/gcc/cp/typeck2.c b/gcc-4.9/gcc/cp/typeck2.c index 68e518a5c..85696f6e0 100644 --- a/gcc-4.9/gcc/cp/typeck2.c +++ b/gcc-4.9/gcc/cp/typeck2.c @@ -1138,7 +1138,7 @@ massage_init_elt (tree type, tree init, tsubst_flags_t complain) /* When we defer constant folding within a statement, we may want to defer this folding as well. */ tree t = fold_non_dependent_expr_sfinae (init, complain); - t = maybe_constant_value (t); + t = maybe_constant_init (t); if (TREE_CONSTANT (t)) init = t; return init; diff --git a/gcc-4.9/gcc/doc/extend.texi b/gcc-4.9/gcc/doc/extend.texi index 347a94a3a..9780d9238 100644 --- a/gcc-4.9/gcc/doc/extend.texi +++ b/gcc-4.9/gcc/doc/extend.texi @@ -12787,9 +12787,12 @@ float __builtin_recipdivf (float, float); float __builtin_rsqrtf (float); double __builtin_recipdiv (double, double); double __builtin_rsqrt (double); -long __builtin_bpermd (long, long); uint64_t __builtin_ppc_get_timebase (); unsigned long __builtin_ppc_mftb (); +double __builtin_unpack_longdouble (long double, int); +double __builtin_longdouble_dw0 (long double); +double __builtin_longdouble_dw1 (long double); +long double __builtin_pack_longdouble (double, double); @end smallexample The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and @@ -12809,6 +12812,57 @@ The @code{__builtin_ppc_mftb} function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. +The following built-in functions are available for the PowerPC family +of processors, starting with ISA 2.06 or later (@option{-mcpu=power7} +or @option{-mpopcntd}): +@smallexample +long __builtin_bpermd (long, long); +int __builtin_divwe (int, int); +int __builtin_divweo (int, int); +unsigned int __builtin_divweu (unsigned int, unsigned int); +unsigned int __builtin_divweuo (unsigned int, unsigned int); +long __builtin_divde (long, long); +long __builtin_divdeo (long, long); +unsigned long __builtin_divdeu (unsigned long, unsigned long); +unsigned long __builtin_divdeuo (unsigned long, unsigned long); +unsigned int cdtbcd (unsigned int); +unsigned int cbcdtd (unsigned int); +unsigned int addg6s (unsigned int, unsigned int); +@end smallexample + +The @code{__builtin_divde}, @code{__builtin_divdeo}, +@code{__builitin_divdeu}, @code{__builtin_divdeou} functions require a +64-bit environment support ISA 2.06 or later. + +The following built-in functions are available for the PowerPC family +of processors when hardware decimal floating point +(@option{-mhard-dfp}) is available: +@smallexample +_Decimal64 __builtin_dxex (_Decimal64); +_Decimal128 __builtin_dxexq (_Decimal128); +_Decimal64 __builtin_ddedpd (int, _Decimal64); +_Decimal128 __builtin_ddedpdq (int, _Decimal128); +_Decimal64 __builtin_denbcd (int, _Decimal64); +_Decimal128 __builtin_denbcdq (int, _Decimal128); +_Decimal64 __builtin_diex (_Decimal64, _Decimal64); +_Decimal128 _builtin_diexq (_Decimal128, _Decimal128); +_Decimal64 __builtin_dscli (_Decimal64, int); +_Decimal128 __builitn_dscliq (_Decimal128, int); +_Decimal64 __builtin_dscri (_Decimal64, int); +_Decimal128 __builitn_dscriq (_Decimal128, int); +unsigned long long __builtin_unpack_dec128 (_Decimal128, int); +_Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long); +@end smallexample + +The following built-in functions are available for the PowerPC family +of processors when the Vector Scalar (vsx) instruction set is +available: +@smallexample +unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int); +vector __int128_t __builtin_pack_vector_int128 (unsigned long long, + unsigned long long); +@end smallexample + @node PowerPC AltiVec/VSX Built-in Functions @subsection PowerPC AltiVec Built-in Functions @@ -15220,6 +15274,17 @@ vector __uint128_t vec_vsubcuq (vector __uint128_t, vector __uint128_t); __int128_t vec_vsubuqm (__int128_t, __int128_t); __uint128_t vec_vsubuqm (__uint128_t, __uint128_t); + +vector __int128_t __builtin_bcdadd (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_lt (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_eq (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_gt (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_ov (vector __int128_t, vector__int128_t); +vector __int128_t bcdsub (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_lt (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_eq (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t); @end smallexample If the cryptographic instructions are enabled (@option{-mcrypto} or diff --git a/gcc-4.9/gcc/doc/install.texi b/gcc-4.9/gcc/doc/install.texi index c32f1f90e..6b45e9d0d 100644 --- a/gcc-4.9/gcc/doc/install.texi +++ b/gcc-4.9/gcc/doc/install.texi @@ -2544,8 +2544,7 @@ Finally a @code{stagefeedback} compiler is built using the information collected Unlike standard bootstrap, several additional restrictions apply. The compiler used to build @code{stage1} needs to support a 64-bit integral type. -It is recommended to only use GCC for this. Also parallel make is currently -not supported since collisions in profile collecting may occur. +It is recommended to only use GCC for this. @html
diff --git a/gcc-4.9/gcc/doc/invoke.texi b/gcc-4.9/gcc/doc/invoke.texi index 8ecb44565..0324a8571 100644 --- a/gcc-4.9/gcc/doc/invoke.texi +++ b/gcc-4.9/gcc/doc/invoke.texi @@ -825,7 +825,8 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-meb -mel -mno-crt0} @emph{MSP430 Options} -@gccoptlist{-msim -masm-hex -mmcu= -mcpu= -mlarge -msmall -mrelax} +@gccoptlist{-msim -masm-hex -mmcu= -mcpu= -mlarge -msmall -mrelax @gol +-mhwmult=} @emph{NDS32 Options} @gccoptlist{-mbig-endian -mlittle-endian @gol @@ -991,6 +992,7 @@ See RS/6000 and PowerPC Options. -mhard-quad-float -msoft-quad-float @gol -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol +-muser-mode -mno-user-mode @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mcbcond -mno-cbcond @gol @@ -18218,6 +18220,28 @@ This option is passed to the assembler and linker, and allows the linker to perform certain optimizations that cannot be done until the final link. +@item mhwmult= +@opindex mhwmult= +Describes the type of hardware multiply supported by the target. +Accepted values are @code{none} for no hardware multiply, @code{16bit} +for the original 16-bit-only multiply supported by early MCUs. +@code{32bit} for the 16/32-bit multiply supported by later MCUs and +@code{f5series} for the 16/32-bit multiply supported by F5-series MCUs. +A value of @code{auto} can also be given. This tells GCC to deduce +the hardware multiply support based upon the MCU name provided by the +@option{-mmcu} option. If no @option{-mmcu} option is specified then +@code{32bit} hardware multiply support is assumed. @code{auto} is the +default setting. + +Hardware multiplies are normally performed by calling a library +routine. This saves space in the generated code. When compiling at +@code{-O3} or higher however the hardware multiplier is invoked +inline. This makes for bigger, but faster code. + +The hardware multiply routines disable interrupts whilst running and +restore the previous interrupt state when they finish. This makes +them safe to use inside interrupt handlers as well as in normal code. + @end table @node NDS32 Options @@ -20908,6 +20932,14 @@ Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +@item -muser-mode +@itemx -mno-user-mode +@opindex muser-mode +@opindex mno-user-mode +Do not generate code that can only run in supervisor mode. This is relevant +only for the @code{casa} instruction emitted for the LEON3 processor. The +default is @option{-mno-user-mode}. + @item -mno-faster-structs @itemx -mfaster-structs @opindex mno-faster-structs diff --git a/gcc-4.9/gcc/doc/sourcebuild.texi b/gcc-4.9/gcc/doc/sourcebuild.texi index 914860813..7438980f0 100644 --- a/gcc-4.9/gcc/doc/sourcebuild.texi +++ b/gcc-4.9/gcc/doc/sourcebuild.texi @@ -1601,6 +1601,13 @@ MIPS target supports @code{-mpaired-single}. @subsubsection PowerPC-specific attributes @table @code + +@item dfp_hw +PowerPC target supports executing hardware DFP instructions. + +@item p8vector_hw +PowerPC target supports executing VSX instructions (ISA 2.07). + @item powerpc64 Test system supports executing 64-bit instructions. @@ -1610,12 +1617,24 @@ PowerPC target supports AltiVec. @item powerpc_altivec_ok PowerPC target supports @code{-maltivec}. +@item powerpc_eabi_ok +PowerPC target supports @code{-meabi}. + +@item powerpc_elfv2 +PowerPC target supports @code{-mabi=elfv2}. + @item powerpc_fprs PowerPC target supports floating-point registers. @item powerpc_hard_double PowerPC target supports hardware double-precision floating-point. +@item powerpc_htm_ok +PowerPC target supports @code{-mhtm} + +@item powerpc_p8vector_ok +PowerPC target supports @code{-mpower8-vector} + @item powerpc_ppu_ok PowerPC target supports @code{-mcpu=cell}. @@ -1629,9 +1648,6 @@ PowerPC target supports PowerPC SPE. @item powerpc_spu PowerPC target supports PowerPC SPU. -@item spu_auto_overlay -SPU target has toolchain that supports automatic overlay generation. - @item powerpc_vsx_ok PowerPC target supports @code{-mvsx}. @@ -1639,8 +1655,17 @@ PowerPC target supports @code{-mvsx}. Including the options used to compile this particular test, the PowerPC target supports PowerPC 405. +@item ppc_recip_hw +PowerPC target supports executing reciprocal estimate instructions. + +@item spu_auto_overlay +SPU target has toolchain that supports automatic overlay generation. + @item vmx_hw PowerPC target supports executing AltiVec instructions. + +@item vsx_hw +PowerPC target supports executing VSX instructions (ISA 2.06). @end table @subsubsection Other hardware attributes diff --git a/gcc-4.9/gcc/fold-const.c b/gcc-4.9/gcc/fold-const.c index 891c0d515..5c2bf256c 100644 --- a/gcc-4.9/gcc/fold-const.c +++ b/gcc-4.9/gcc/fold-const.c @@ -484,8 +484,6 @@ negate_expr_p (tree t) case TRUNC_DIV_EXPR: case ROUND_DIV_EXPR: - case FLOOR_DIV_EXPR: - case CEIL_DIV_EXPR: case EXACT_DIV_EXPR: /* In general we can't negate A / B, because if A is INT_MIN and B is 1, we may turn this into INT_MIN / -1 which is undefined @@ -682,8 +680,6 @@ fold_negate_expr (location_t loc, tree t) case TRUNC_DIV_EXPR: case ROUND_DIV_EXPR: - case FLOOR_DIV_EXPR: - case CEIL_DIV_EXPR: case EXACT_DIV_EXPR: /* In general we can't negate A / B, because if A is INT_MIN and B is 1, we may turn this into INT_MIN / -1 which is undefined diff --git a/gcc-4.9/gcc/fortran/ChangeLog b/gcc-4.9/gcc/fortran/ChangeLog index eb33cc928..42f0321c5 100644 --- a/gcc-4.9/gcc/fortran/ChangeLog +++ b/gcc-4.9/gcc/fortran/ChangeLog @@ -1,3 +1,13 @@ +2014-04-22 Tobias Burnus + + Backport from mainline + 2014-04-11 Tobias Burnus + + PR fortran/58880 + PR fortran/60495 + * resolve.c (gfc_resolve_finalizers): Ensure that vtables + and finalization wrappers are generated. + 2014-04-22 Release Manager * GCC 4.9.0 released. diff --git a/gcc-4.9/gcc/fortran/resolve.c b/gcc-4.9/gcc/fortran/resolve.c index 6e23e570b..38755fef6 100644 --- a/gcc-4.9/gcc/fortran/resolve.c +++ b/gcc-4.9/gcc/fortran/resolve.c @@ -11200,15 +11200,36 @@ resolve_fl_procedure (gfc_symbol *sym, int mp_flag) the requirements of the standard for procedures used as finalizers. */ static bool -gfc_resolve_finalizers (gfc_symbol* derived) +gfc_resolve_finalizers (gfc_symbol* derived, bool *finalizable) { gfc_finalizer* list; gfc_finalizer** prev_link; /* For removing wrong entries from the list. */ bool result = true; bool seen_scalar = false; + gfc_symbol *vtab; + gfc_component *c; + /* Return early when not finalizable. Additionally, ensure that derived-type + components have a their finalizables resolved. */ if (!derived->f2k_derived || !derived->f2k_derived->finalizers) - return true; + { + bool has_final = false; + for (c = derived->components; c; c = c->next) + if (c->ts.type == BT_DERIVED + && !c->attr.pointer && !c->attr.proc_pointer && !c->attr.allocatable) + { + bool has_final2 = false; + if (!gfc_resolve_finalizers (c->ts.u.derived, &has_final)) + return false; /* Error. */ + has_final = has_final || has_final2; + } + if (!has_final) + { + if (finalizable) + *finalizable = false; + return true; + } + } /* Walk over the list of finalizer-procedures, check them, and if any one does not fit in with the standard's definition, print an error and remove @@ -11330,12 +11351,15 @@ gfc_resolve_finalizers (gfc_symbol* derived) /* Remove wrong nodes immediately from the list so we don't risk any troubles in the future when they might fail later expectations. */ error: - result = false; i = list; *prev_link = list->next; gfc_free_finalizer (i); + result = false; } + if (result == false) + return false; + /* Warn if we haven't seen a scalar finalizer procedure (but we know there were nodes in the list, must have been for arrays. It is surely a good idea to have a scalar version there if there's something to finalize. */ @@ -11344,8 +11368,14 @@ error: " defined at %L, suggest also scalar one", derived->name, &derived->declared_at); - gfc_find_derived_vtab (derived); - return result; + vtab = gfc_find_derived_vtab (derived); + c = vtab->ts.u.derived->components->next->next->next->next->next; + gfc_set_sym_referenced (c->initializer->symtree->n.sym); + + if (finalizable) + *finalizable = true; + + return true; } @@ -12513,7 +12543,7 @@ resolve_fl_derived (gfc_symbol *sym) return false; /* Resolve the finalizer procedures. */ - if (!gfc_resolve_finalizers (sym)) + if (!gfc_resolve_finalizers (sym, NULL)) return false; if (sym->attr.is_class && sym->ts.u.derived == NULL) diff --git a/gcc-4.9/gcc/gimple-ssa-strength-reduction.c b/gcc-4.9/gcc/gimple-ssa-strength-reduction.c index 9ad1b4f06..cb19399bd 100644 --- a/gcc-4.9/gcc/gimple-ssa-strength-reduction.c +++ b/gcc-4.9/gcc/gimple-ssa-strength-reduction.c @@ -1114,15 +1114,18 @@ create_mul_imm_cand (gimple gs, tree base_in, tree stride_in, bool speed) X = Y * c ============================ X = (B + i') * (S * c) */ - base = base_cand->base_expr; - index = base_cand->index; temp = tree_to_double_int (base_cand->stride) * tree_to_double_int (stride_in); - stride = double_int_to_tree (TREE_TYPE (stride_in), temp); - ctype = base_cand->cand_type; - if (has_single_use (base_in)) - savings = (base_cand->dead_savings - + stmt_cost (base_cand->cand_stmt, speed)); + if (double_int_fits_to_tree_p (TREE_TYPE (stride_in), temp)) + { + base = base_cand->base_expr; + index = base_cand->index; + stride = double_int_to_tree (TREE_TYPE (stride_in), temp); + ctype = base_cand->cand_type; + if (has_single_use (base_in)) + savings = (base_cand->dead_savings + + stmt_cost (base_cand->cand_stmt, speed)); + } } else if (base_cand->kind == CAND_ADD && integer_onep (base_cand->stride)) { diff --git a/gcc-4.9/gcc/gimplify.c b/gcc-4.9/gcc/gimplify.c index dcc2d74bc..9f4bad853 100644 --- a/gcc-4.9/gcc/gimplify.c +++ b/gcc-4.9/gcc/gimplify.c @@ -5802,7 +5802,7 @@ omp_notice_variable (struct gimplify_omp_ctx *ctx, tree decl, bool in_code) to the contrary in the innermost scope, generate an error. */ static bool -omp_is_private (struct gimplify_omp_ctx *ctx, tree decl, bool simd) +omp_is_private (struct gimplify_omp_ctx *ctx, tree decl, int simd) { splay_tree_node n; @@ -5836,13 +5836,13 @@ omp_is_private (struct gimplify_omp_ctx *ctx, tree decl, bool simd) else if ((n->value & GOVD_REDUCTION) != 0) error ("iteration variable %qE should not be reduction", DECL_NAME (decl)); - else if (simd && (n->value & GOVD_LASTPRIVATE) != 0) + else if (simd == 1 && (n->value & GOVD_LASTPRIVATE) != 0) error ("iteration variable %qE should not be lastprivate", DECL_NAME (decl)); else if (simd && (n->value & GOVD_PRIVATE) != 0) error ("iteration variable %qE should not be private", DECL_NAME (decl)); - else if (simd && (n->value & GOVD_LINEAR) != 0) + else if (simd == 2 && (n->value & GOVD_LINEAR) != 0) error ("iteration variable %qE is predetermined linear", DECL_NAME (decl)); } @@ -6279,9 +6279,17 @@ gimplify_adjust_omp_clauses_1 (splay_tree_node n, void *data) OMP_CLAUSE_CHAIN (clause) = nc; } } + if (code == OMP_CLAUSE_FIRSTPRIVATE && (flags & GOVD_LASTPRIVATE) != 0) + { + tree nc = build_omp_clause (input_location, OMP_CLAUSE_LASTPRIVATE); + OMP_CLAUSE_DECL (nc) = decl; + OMP_CLAUSE_LASTPRIVATE_FIRSTPRIVATE (nc) = 1; + OMP_CLAUSE_CHAIN (nc) = *list_p; + OMP_CLAUSE_CHAIN (clause) = nc; + lang_hooks.decls.omp_finish_clause (nc); + } *list_p = clause; lang_hooks.decls.omp_finish_clause (clause); - return 0; } @@ -6320,18 +6328,17 @@ gimplify_adjust_omp_clauses (tree *list_p) if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LINEAR && ctx->outer_context && !(OMP_CLAUSE_LINEAR_NO_COPYIN (c) - && OMP_CLAUSE_LINEAR_NO_COPYOUT (c)) - && !is_global_var (decl)) + && OMP_CLAUSE_LINEAR_NO_COPYOUT (c))) { - if (ctx->outer_context->region_type == ORT_COMBINED_PARALLEL) + if (ctx->outer_context->combined_loop + && !OMP_CLAUSE_LINEAR_NO_COPYIN (c)) { n = splay_tree_lookup (ctx->outer_context->variables, (splay_tree_key) decl); if (n == NULL || (n->value & GOVD_DATA_SHARE_CLASS) == 0) { - int flags = OMP_CLAUSE_LINEAR_NO_COPYIN (c) - ? GOVD_LASTPRIVATE : GOVD_SHARED; + int flags = GOVD_FIRSTPRIVATE | GOVD_LASTPRIVATE; if (n == NULL) omp_add_variable (ctx->outer_context, decl, flags | GOVD_SEEN); @@ -6339,7 +6346,7 @@ gimplify_adjust_omp_clauses (tree *list_p) n->value |= flags | GOVD_SEEN; } } - else + else if (!is_global_var (decl)) omp_notice_variable (ctx->outer_context, decl, true); } } @@ -6608,8 +6615,8 @@ gimplify_omp_for (tree *expr_p, gimple_seq *pre_p) orig_for_stmt = for_stmt = *expr_p; - simd = TREE_CODE (for_stmt) == OMP_SIMD - || TREE_CODE (for_stmt) == CILK_SIMD; + simd = (TREE_CODE (for_stmt) == OMP_SIMD + || TREE_CODE (for_stmt) == CILK_SIMD); gimplify_scan_omp_clauses (&OMP_FOR_CLAUSES (for_stmt), pre_p, simd ? ORT_SIMD : ORT_WORKSHARE); @@ -6665,13 +6672,16 @@ gimplify_omp_for (tree *expr_p, gimple_seq *pre_p) /* Make sure the iteration variable is private. */ tree c = NULL_TREE; + tree c2 = NULL_TREE; if (orig_for_stmt != for_stmt) /* Do this only on innermost construct for combined ones. */; else if (simd) { splay_tree_node n = splay_tree_lookup (gimplify_omp_ctxp->variables, (splay_tree_key)decl); - omp_is_private (gimplify_omp_ctxp, decl, simd); + omp_is_private (gimplify_omp_ctxp, decl, + 1 + (TREE_VEC_LENGTH (OMP_FOR_INIT (for_stmt)) + != 1)); if (n != NULL && (n->value & GOVD_DATA_SHARE_CLASS) != 0) omp_notice_variable (gimplify_omp_ctxp, decl, true); else if (TREE_VEC_LENGTH (OMP_FOR_INIT (for_stmt)) == 1) @@ -6697,13 +6707,14 @@ gimplify_omp_for (tree *expr_p, gimple_seq *pre_p) : OMP_CLAUSE_PRIVATE); OMP_CLAUSE_DECL (c) = decl; OMP_CLAUSE_CHAIN (c) = OMP_FOR_CLAUSES (for_stmt); + OMP_FOR_CLAUSES (for_stmt) = c; omp_add_variable (gimplify_omp_ctxp, decl, (lastprivate ? GOVD_LASTPRIVATE : GOVD_PRIVATE) - | GOVD_SEEN); + | GOVD_EXPLICIT | GOVD_SEEN); c = NULL_TREE; } } - else if (omp_is_private (gimplify_omp_ctxp, decl, simd)) + else if (omp_is_private (gimplify_omp_ctxp, decl, 0)) omp_notice_variable (gimplify_omp_ctxp, decl, true); else omp_add_variable (gimplify_omp_ctxp, decl, GOVD_PRIVATE | GOVD_SEEN); @@ -6720,7 +6731,25 @@ gimplify_omp_for (tree *expr_p, gimple_seq *pre_p) gimplify_seq_add_stmt (&for_body, gimple_build_assign (decl, var)); - omp_add_variable (gimplify_omp_ctxp, var, GOVD_PRIVATE | GOVD_SEEN); + if (simd && TREE_VEC_LENGTH (OMP_FOR_INIT (for_stmt)) == 1) + { + c2 = build_omp_clause (input_location, OMP_CLAUSE_LINEAR); + OMP_CLAUSE_LINEAR_NO_COPYIN (c2) = 1; + OMP_CLAUSE_LINEAR_NO_COPYOUT (c2) = 1; + OMP_CLAUSE_DECL (c2) = var; + OMP_CLAUSE_CHAIN (c2) = OMP_FOR_CLAUSES (for_stmt); + OMP_FOR_CLAUSES (for_stmt) = c2; + omp_add_variable (gimplify_omp_ctxp, var, + GOVD_LINEAR | GOVD_EXPLICIT | GOVD_SEEN); + if (c == NULL_TREE) + { + c = c2; + c2 = NULL_TREE; + } + } + else + omp_add_variable (gimplify_omp_ctxp, var, + GOVD_PRIVATE | GOVD_SEEN); } else var = decl; @@ -6823,13 +6852,22 @@ gimplify_omp_for (tree *expr_p, gimple_seq *pre_p) gcc_unreachable (); } + if (c2) + { + gcc_assert (c); + OMP_CLAUSE_LINEAR_STEP (c2) = OMP_CLAUSE_LINEAR_STEP (c); + } + if ((var != decl || TREE_VEC_LENGTH (OMP_FOR_INIT (for_stmt)) > 1) && orig_for_stmt == for_stmt) { for (c = OMP_FOR_CLAUSES (for_stmt); c ; c = OMP_CLAUSE_CHAIN (c)) - if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LASTPRIVATE - && OMP_CLAUSE_DECL (c) == decl - && OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c) == NULL) + if (((OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LASTPRIVATE + && OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c) == NULL) + || (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LINEAR + && !OMP_CLAUSE_LINEAR_NO_COPYOUT (c) + && OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c) == NULL)) + && OMP_CLAUSE_DECL (c) == decl) { t = TREE_VEC_ELT (OMP_FOR_INCR (for_stmt), i); gcc_assert (TREE_CODE (t) == MODIFY_EXPR); @@ -6841,8 +6879,12 @@ gimplify_omp_for (tree *expr_p, gimple_seq *pre_p) gcc_assert (TREE_OPERAND (t, 0) == var); t = build2 (TREE_CODE (t), TREE_TYPE (decl), decl, TREE_OPERAND (t, 1)); - gimplify_assign (decl, t, - &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c)); + gimple_seq *seq; + if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LASTPRIVATE) + seq = &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c); + else + seq = &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c); + gimplify_assign (decl, t, seq); } } } diff --git a/gcc-4.9/gcc/go/gofrontend/import-archive.cc b/gcc-4.9/gcc/go/gofrontend/import-archive.cc index 9a1d5b3d7..34fb528ab 100644 --- a/gcc-4.9/gcc/go/gofrontend/import-archive.cc +++ b/gcc-4.9/gcc/go/gofrontend/import-archive.cc @@ -261,7 +261,7 @@ Archive_file::interpret_header(const Archive_header* hdr, off_t off, char size_string[size_string_size + 1]; memcpy(size_string, hdr->ar_size, size_string_size); char* ps = size_string + size_string_size; - while (ps[-1] == ' ') + while (ps > size_string && ps[-1] == ' ') --ps; *ps = '\0'; diff --git a/gcc-4.9/gcc/go/gofrontend/types.cc b/gcc-4.9/gcc/go/gofrontend/types.cc index 2148a1a43..e79adb396 100644 --- a/gcc-4.9/gcc/go/gofrontend/types.cc +++ b/gcc-4.9/gcc/go/gofrontend/types.cc @@ -8966,9 +8966,8 @@ Type::finalize_methods(Gogo* gogo, const Type* type, Location location, Methods** all_methods) { *all_methods = NULL; - Types_seen types_seen; - Type::add_methods_for_type(type, NULL, 0, false, false, &types_seen, - all_methods); + std::vector seen; + Type::add_methods_for_type(type, NULL, 0, false, false, &seen, all_methods); Type::build_stub_methods(gogo, type, *all_methods, location); } @@ -8986,7 +8985,7 @@ Type::add_methods_for_type(const Type* type, unsigned int depth, bool is_embedded_pointer, bool needs_stub_method, - Types_seen* types_seen, + std::vector* seen, Methods** methods) { // Pointer types may not have methods. @@ -8996,19 +8995,24 @@ Type::add_methods_for_type(const Type* type, const Named_type* nt = type->named_type(); if (nt != NULL) { - std::pair ins = types_seen->insert(nt); - if (!ins.second) - return; - } + for (std::vector::const_iterator p = seen->begin(); + p != seen->end(); + ++p) + { + if (*p == nt) + return; + } - if (nt != NULL) - Type::add_local_methods_for_type(nt, field_indexes, depth, - is_embedded_pointer, needs_stub_method, - methods); + seen->push_back(nt); + + Type::add_local_methods_for_type(nt, field_indexes, depth, + is_embedded_pointer, needs_stub_method, + methods); + } Type::add_embedded_methods_for_type(type, field_indexes, depth, is_embedded_pointer, needs_stub_method, - types_seen, methods); + seen, methods); // If we are called with depth > 0, then we are looking at an // anonymous field of a struct. If such a field has interface type, @@ -9017,6 +9021,9 @@ Type::add_methods_for_type(const Type* type, // following the usual rules for an interface type. if (depth > 0) Type::add_interface_methods_for_type(type, field_indexes, depth, methods); + + if (nt != NULL) + seen->pop_back(); } // Add the local methods for the named type NT to *METHODS. The @@ -9062,7 +9069,7 @@ Type::add_embedded_methods_for_type(const Type* type, unsigned int depth, bool is_embedded_pointer, bool needs_stub_method, - Types_seen* types_seen, + std::vector* seen, Methods** methods) { // Look for anonymous fields in TYPE. TYPE has fields if it is a @@ -9106,7 +9113,7 @@ Type::add_embedded_methods_for_type(const Type* type, (needs_stub_method || is_pointer || i > 0), - types_seen, + seen, methods); } } diff --git a/gcc-4.9/gcc/go/gofrontend/types.h b/gcc-4.9/gcc/go/gofrontend/types.h index 5fda4e728..acb06cac5 100644 --- a/gcc-4.9/gcc/go/gofrontend/types.h +++ b/gcc-4.9/gcc/go/gofrontend/types.h @@ -1171,14 +1171,11 @@ class Type static tree build_receive_return_type(tree type); - // A hash table we use to avoid infinite recursion. - typedef Unordered_set_hash(const Named_type*, Type_hash_identical, - Type_identical) Types_seen; - // Add all methods for TYPE to the list of methods for THIS. static void add_methods_for_type(const Type* type, const Method::Field_indexes*, - unsigned int depth, bool, bool, Types_seen*, + unsigned int depth, bool, bool, + std::vector*, Methods**); static void @@ -1189,7 +1186,8 @@ class Type static void add_embedded_methods_for_type(const Type* type, const Method::Field_indexes*, - unsigned int depth, bool, bool, Types_seen*, + unsigned int depth, bool, bool, + std::vector*, Methods**); static void diff --git a/gcc-4.9/gcc/graphite-scop-detection.c b/gcc-4.9/gcc/graphite-scop-detection.c index b5e4a8c8c..821f0846e 100644 --- a/gcc-4.9/gcc/graphite-scop-detection.c +++ b/gcc-4.9/gcc/graphite-scop-detection.c @@ -219,7 +219,14 @@ graphite_can_represent_scev (tree scev) switch (TREE_CODE (scev)) { + case NEGATE_EXPR: + case BIT_NOT_EXPR: + CASE_CONVERT: + case NON_LVALUE_EXPR: + return graphite_can_represent_scev (TREE_OPERAND (scev, 0)); + case PLUS_EXPR: + case POINTER_PLUS_EXPR: case MINUS_EXPR: return graphite_can_represent_scev (TREE_OPERAND (scev, 0)) && graphite_can_represent_scev (TREE_OPERAND (scev, 1)); @@ -241,13 +248,15 @@ graphite_can_represent_scev (tree scev) if (!evolution_function_right_is_integer_cst (scev) || !graphite_can_represent_init (scev)) return false; + return graphite_can_represent_scev (CHREC_LEFT (scev)); default: break; } /* Only affine functions can be represented. */ - if (!scev_is_linear_expression (scev)) + if (tree_contains_chrecs (scev, NULL) + || !scev_is_linear_expression (scev)) return false; return true; diff --git a/gcc-4.9/gcc/ipa-devirt.c b/gcc-4.9/gcc/ipa-devirt.c index 03a6c5b5d..7f07d2f94 100644 --- a/gcc-4.9/gcc/ipa-devirt.c +++ b/gcc-4.9/gcc/ipa-devirt.c @@ -987,6 +987,17 @@ give_up: context->outer_type = expected_type; context->offset = 0; context->maybe_derived_type = true; + context->maybe_in_construction = true; + /* POD can be changed to an instance of a polymorphic type by + placement new. Here we play safe and assume that any + non-polymorphic type is POD. */ + if ((TREE_CODE (type) != RECORD_TYPE + || !TYPE_BINFO (type) + || !polymorphic_type_binfo_p (TYPE_BINFO (type))) + && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST + || (offset + tree_to_uhwi (TYPE_SIZE (expected_type)) <= + tree_to_uhwi (TYPE_SIZE (type))))) + return true; return false; } diff --git a/gcc-4.9/gcc/loop-init.c b/gcc-4.9/gcc/loop-init.c index 2c2c269b8..4cc561c2e 100644 --- a/gcc-4.9/gcc/loop-init.c +++ b/gcc-4.9/gcc/loop-init.c @@ -94,20 +94,15 @@ loop_optimizer_init (unsigned flags) else { bool recorded_exits = loops_state_satisfies_p (LOOPS_HAVE_RECORDED_EXITS); + bool needs_fixup = loops_state_satisfies_p (LOOPS_NEED_FIXUP); gcc_assert (cfun->curr_properties & PROP_loops); /* Ensure that the dominators are computed, like flow_loops_find does. */ calculate_dominance_info (CDI_DOMINATORS); - if (loops_state_satisfies_p (LOOPS_NEED_FIXUP)) - { - loops_state_clear (~0U); - fix_loop_structure (NULL); - } - #ifdef ENABLE_CHECKING - else + if (!needs_fixup) verify_loop_structure (); #endif @@ -115,6 +110,14 @@ loop_optimizer_init (unsigned flags) if (recorded_exits) release_recorded_exits (); loops_state_clear (~0U); + + if (needs_fixup) + { + /* Apply LOOPS_MAY_HAVE_MULTIPLE_LATCHES early as fix_loop_structure + re-applies flags. */ + loops_state_set (flags & LOOPS_MAY_HAVE_MULTIPLE_LATCHES); + fix_loop_structure (NULL); + } } /* Apply flags to loops. */ diff --git a/gcc-4.9/gcc/lto-streamer-out.c b/gcc-4.9/gcc/lto-streamer-out.c index 69b5a79e5..b193d730d 100644 --- a/gcc-4.9/gcc/lto-streamer-out.c +++ b/gcc-4.9/gcc/lto-streamer-out.c @@ -2022,6 +2022,29 @@ copy_function (struct cgraph_node *node) lto_end_section (); } +/* Wrap symbol references in *TP inside a type-preserving MEM_REF. */ + +static tree +wrap_refs (tree *tp, int *ws, void *) +{ + tree t = *tp; + if (handled_component_p (t) + && TREE_CODE (TREE_OPERAND (t, 0)) == VAR_DECL) + { + tree decl = TREE_OPERAND (t, 0); + tree ptrtype = build_pointer_type (TREE_TYPE (decl)); + TREE_OPERAND (t, 0) = build2 (MEM_REF, TREE_TYPE (decl), + build1 (ADDR_EXPR, ptrtype, decl), + build_int_cst (ptrtype, 0)); + TREE_THIS_VOLATILE (TREE_OPERAND (t, 0)) = TREE_THIS_VOLATILE (decl); + *ws = 0; + } + else if (TREE_CODE (t) == CONSTRUCTOR) + ; + else if (!EXPR_P (t)) + *ws = 0; + return NULL_TREE; +} /* Main entry point from the pass manager. */ @@ -2043,24 +2066,33 @@ lto_output (void) for (i = 0; i < n_nodes; i++) { symtab_node *snode = lto_symtab_encoder_deref (encoder, i); - cgraph_node *node = dyn_cast (snode); - if (node - && lto_symtab_encoder_encode_body_p (encoder, node) - && !node->alias) + if (cgraph_node *node = dyn_cast (snode)) { + if (lto_symtab_encoder_encode_body_p (encoder, node) + && !node->alias) + { #ifdef ENABLE_CHECKING - gcc_assert (!bitmap_bit_p (output, DECL_UID (node->decl))); - bitmap_set_bit (output, DECL_UID (node->decl)); + gcc_assert (!bitmap_bit_p (output, DECL_UID (node->decl))); + bitmap_set_bit (output, DECL_UID (node->decl)); #endif - decl_state = lto_new_out_decl_state (); - lto_push_out_decl_state (decl_state); - if (gimple_has_body_p (node->decl) || !flag_wpa) - output_function (node); - else - copy_function (node); - gcc_assert (lto_get_out_decl_state () == decl_state); - lto_pop_out_decl_state (); - lto_record_function_out_decl_state (node->decl, decl_state); + decl_state = lto_new_out_decl_state (); + lto_push_out_decl_state (decl_state); + if (gimple_has_body_p (node->decl) || !flag_wpa) + output_function (node); + else + copy_function (node); + gcc_assert (lto_get_out_decl_state () == decl_state); + lto_pop_out_decl_state (); + lto_record_function_out_decl_state (node->decl, decl_state); + } + } + else if (varpool_node *node = dyn_cast (snode)) + { + /* Wrap symbol references inside the ctor in a type + preserving MEM_REF. */ + tree ctor = DECL_INITIAL (node->decl); + if (ctor && !in_lto_p) + walk_tree (&ctor, wrap_refs, NULL, NULL); } } diff --git a/gcc-4.9/gcc/omp-low.c b/gcc-4.9/gcc/omp-low.c index 11bb2d35a..26e484964 100644 --- a/gcc-4.9/gcc/omp-low.c +++ b/gcc-4.9/gcc/omp-low.c @@ -1730,6 +1730,9 @@ scan_sharing_clauses (tree clauses, omp_context *ctx) if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_REDUCTION && OMP_CLAUSE_REDUCTION_PLACEHOLDER (c)) scan_array_reductions = true; + else if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LINEAR + && OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c)) + scan_array_reductions = true; break; case OMP_CLAUSE_SHARED: @@ -1816,6 +1819,9 @@ scan_sharing_clauses (tree clauses, omp_context *ctx) else if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LASTPRIVATE && OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c)) scan_omp (&OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c), ctx); + else if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LINEAR + && OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c)) + scan_omp (&OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c), ctx); } /* Create a new name for omp child function. Returns an identifier. */ @@ -3803,6 +3809,14 @@ lower_lastprivate_clauses (tree clauses, tree predicate, gimple_seq *stmt_list, OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c)); OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (c) = NULL; } + else if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_LINEAR + && OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c)) + { + lower_omp (&OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c), ctx); + gimple_seq_add_seq (stmt_list, + OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c)); + OMP_CLAUSE_LINEAR_GIMPLE_SEQ (c) = NULL; + } x = build_outer_var_ref (var, ctx); if (is_reference (var)) @@ -5570,6 +5584,12 @@ expand_omp_for_generic (struct omp_region *region, { stmt = gimple_build_assign (endvar, iend); gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING); + if (useless_type_conversion_p (TREE_TYPE (fd->loop.v), TREE_TYPE (iend))) + stmt = gimple_build_assign (fd->loop.v, iend); + else + stmt = gimple_build_assign_with_ops (NOP_EXPR, fd->loop.v, iend, + NULL_TREE); + gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING); } if (fd->collapse > 1) expand_omp_for_init_vars (fd, &gsi, counts, inner_stmt, startvar); @@ -5986,6 +6006,12 @@ expand_omp_for_static_nochunk (struct omp_region *region, { stmt = gimple_build_assign (endvar, e); gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING); + if (useless_type_conversion_p (TREE_TYPE (fd->loop.v), TREE_TYPE (e))) + stmt = gimple_build_assign (fd->loop.v, e); + else + stmt = gimple_build_assign_with_ops (NOP_EXPR, fd->loop.v, e, + NULL_TREE); + gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING); } if (fd->collapse > 1) expand_omp_for_init_vars (fd, &gsi, counts, inner_stmt, startvar); @@ -6371,6 +6397,12 @@ expand_omp_for_static_chunk (struct omp_region *region, { stmt = gimple_build_assign (endvar, e); gsi_insert_after (&si, stmt, GSI_CONTINUE_LINKING); + if (useless_type_conversion_p (TREE_TYPE (fd->loop.v), TREE_TYPE (e))) + stmt = gimple_build_assign (fd->loop.v, e); + else + stmt = gimple_build_assign_with_ops (NOP_EXPR, fd->loop.v, e, + NULL_TREE); + gsi_insert_after (&si, stmt, GSI_CONTINUE_LINKING); } if (fd->collapse > 1) expand_omp_for_init_vars (fd, &si, counts, inner_stmt, startvar); @@ -11291,45 +11323,53 @@ static tree ipa_simd_modify_stmt_ops (tree *tp, int *walk_subtrees, void *data) { struct walk_stmt_info *wi = (struct walk_stmt_info *) data; - if (!SSA_VAR_P (*tp)) + struct modify_stmt_info *info = (struct modify_stmt_info *) wi->info; + tree *orig_tp = tp; + if (TREE_CODE (*tp) == ADDR_EXPR) + tp = &TREE_OPERAND (*tp, 0); + struct ipa_parm_adjustment *cand = NULL; + if (TREE_CODE (*tp) == PARM_DECL) + cand = ipa_get_adjustment_candidate (&tp, NULL, info->adjustments, true); + else { - /* Make sure we treat subtrees as a RHS. This makes sure that - when examining the `*foo' in *foo=x, the `foo' get treated as - a use properly. */ - wi->is_lhs = false; - wi->val_only = true; if (TYPE_P (*tp)) *walk_subtrees = 0; - return NULL_TREE; } - struct modify_stmt_info *info = (struct modify_stmt_info *) wi->info; - struct ipa_parm_adjustment *cand - = ipa_get_adjustment_candidate (&tp, NULL, info->adjustments, true); - if (!cand) - return NULL_TREE; - tree t = *tp; - tree repl = make_ssa_name (TREE_TYPE (t), NULL); - - gimple stmt; - gimple_stmt_iterator gsi = gsi_for_stmt (info->stmt); - if (wi->is_lhs) + tree repl = NULL_TREE; + if (cand) + repl = unshare_expr (cand->new_decl); + else { - stmt = gimple_build_assign (unshare_expr (cand->new_decl), repl); - gsi_insert_after (&gsi, stmt, GSI_SAME_STMT); - SSA_NAME_DEF_STMT (repl) = info->stmt; + if (tp != orig_tp) + { + *walk_subtrees = 0; + bool modified = info->modified; + info->modified = false; + walk_tree (tp, ipa_simd_modify_stmt_ops, wi, wi->pset); + if (!info->modified) + { + info->modified = modified; + return NULL_TREE; + } + info->modified = modified; + repl = *tp; + } + else + return NULL_TREE; } - else + + if (tp != orig_tp) { - /* You'd think we could skip the extra SSA variable when - wi->val_only=true, but we may have `*var' which will get - replaced into `*var_array[iter]' and will likely be something - not gimple. */ - stmt = gimple_build_assign (repl, unshare_expr (cand->new_decl)); + repl = build_fold_addr_expr (repl); + gimple stmt + = gimple_build_assign (make_ssa_name (TREE_TYPE (repl), NULL), repl); + repl = gimple_assign_lhs (stmt); + gimple_stmt_iterator gsi = gsi_for_stmt (info->stmt); gsi_insert_before (&gsi, stmt, GSI_SAME_STMT); + *orig_tp = repl; } - - if (!useless_type_conversion_p (TREE_TYPE (*tp), TREE_TYPE (repl))) + else if (!useless_type_conversion_p (TREE_TYPE (*tp), TREE_TYPE (repl))) { tree vce = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (*tp), repl); *tp = vce; @@ -11338,8 +11378,6 @@ ipa_simd_modify_stmt_ops (tree *tp, int *walk_subtrees, void *data) *tp = repl; info->modified = true; - wi->is_lhs = false; - wi->val_only = true; return NULL_TREE; } @@ -11358,7 +11396,7 @@ ipa_simd_modify_function_body (struct cgraph_node *node, tree retval_array, tree iter) { basic_block bb; - unsigned int i, j; + unsigned int i, j, l; /* Re-use the adjustments array, but this time use it to replace every function argument use to an offset into the corresponding @@ -11381,6 +11419,46 @@ ipa_simd_modify_function_body (struct cgraph_node *node, j += node->simdclone->simdlen / TYPE_VECTOR_SUBPARTS (vectype) - 1; } + l = adjustments.length (); + for (i = 1; i < num_ssa_names; i++) + { + tree name = ssa_name (i); + if (name + && SSA_NAME_VAR (name) + && TREE_CODE (SSA_NAME_VAR (name)) == PARM_DECL) + { + for (j = 0; j < l; j++) + if (SSA_NAME_VAR (name) == adjustments[j].base + && adjustments[j].new_decl) + { + tree base_var; + if (adjustments[j].new_ssa_base == NULL_TREE) + { + base_var + = copy_var_decl (adjustments[j].base, + DECL_NAME (adjustments[j].base), + TREE_TYPE (adjustments[j].base)); + adjustments[j].new_ssa_base = base_var; + } + else + base_var = adjustments[j].new_ssa_base; + if (SSA_NAME_IS_DEFAULT_DEF (name)) + { + bb = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)); + gimple_stmt_iterator gsi = gsi_after_labels (bb); + tree new_decl = unshare_expr (adjustments[j].new_decl); + set_ssa_default_def (cfun, adjustments[j].base, NULL_TREE); + SET_SSA_NAME_VAR_OR_IDENTIFIER (name, base_var); + SSA_NAME_IS_DEFAULT_DEF (name) = 0; + gimple stmt = gimple_build_assign (name, new_decl); + gsi_insert_before (&gsi, stmt, GSI_SAME_STMT); + } + else + SET_SSA_NAME_VAR_OR_IDENTIFIER (name, base_var); + } + } + } + struct modify_stmt_info info; info.adjustments = adjustments; diff --git a/gcc-4.9/gcc/opts.c b/gcc-4.9/gcc/opts.c index d6c254802..506ed8490 100644 --- a/gcc-4.9/gcc/opts.c +++ b/gcc-4.9/gcc/opts.c @@ -431,8 +431,8 @@ static const struct default_options default_options_table[] = { OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fcprop_registers, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fforward_propagate, NULL, 1 }, - { OPT_LEVELS_1_PLUS, OPT_fif_conversion, NULL, 1 }, - { OPT_LEVELS_1_PLUS, OPT_fif_conversion2, NULL, 1 }, + { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion, NULL, 1 }, + { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion2, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fipa_pure_const, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fipa_reference, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fipa_profile, NULL, 1 }, @@ -1501,9 +1501,9 @@ common_handle_option (struct gcc_options *opts, } if (! found) - warning_at (loc, 0, - "unrecognized argument to -fsanitize= option: %q.*s", - (int) len, p); + error_at (loc, + "unrecognized argument to -fsanitize= option: %q.*s", + (int) len, p); if (comma == NULL) break; diff --git a/gcc-4.9/gcc/passes.c b/gcc-4.9/gcc/passes.c index 60fb13536..377b2471a 100644 --- a/gcc-4.9/gcc/passes.c +++ b/gcc-4.9/gcc/passes.c @@ -2109,20 +2109,6 @@ execute_all_ipa_transforms (void) } } -/* Callback for do_per_function to apply all IPA transforms. */ - -static void -apply_ipa_transforms (void *data) -{ - struct cgraph_node *node = cgraph_get_node (current_function_decl); - if (!node->global.inlined_to && node->ipa_transforms_to_apply.exists ()) - { - *(bool *)data = true; - execute_all_ipa_transforms (); - rebuild_cgraph_edges (); - } -} - /* Check if PASS is explicitly disabled or enabled and return the gate status. FUNC is the function to be processed, and GATE_STATUS is the gate status determined by pass manager by @@ -2194,8 +2180,26 @@ execute_one_pass (opt_pass *pass) Apply all trnasforms first. */ if (pass->type == SIMPLE_IPA_PASS) { + struct cgraph_node *node; bool applied = false; - do_per_function (apply_ipa_transforms, (void *)&applied); + FOR_EACH_DEFINED_FUNCTION (node) + if (node->analyzed + && cgraph_function_with_gimple_body_p (node) + && (!node->clone_of || node->decl != node->clone_of->decl)) + { + if (!node->global.inlined_to + && node->ipa_transforms_to_apply.exists ()) + { + cgraph_get_body (node); + push_cfun (DECL_STRUCT_FUNCTION (node->decl)); + execute_all_ipa_transforms (); + rebuild_cgraph_edges (); + free_dominance_info (CDI_DOMINATORS); + free_dominance_info (CDI_POST_DOMINATORS); + pop_cfun (); + applied = true; + } + } if (applied) symtab_remove_unreachable_nodes (true, dump_file); /* Restore current_pass. */ diff --git a/gcc-4.9/gcc/po/ChangeLog b/gcc-4.9/gcc/po/ChangeLog index b7e3dfb78..d9af0fe34 100644 --- a/gcc-4.9/gcc/po/ChangeLog +++ b/gcc-4.9/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2014-05-01 Joseph Myers + + * sv.po: Update. + 2014-04-22 Release Manager * GCC 4.9.0 released. diff --git a/gcc-4.9/gcc/po/sv.po b/gcc-4.9/gcc/po/sv.po index 0bae3b6f7..b38f70811 100644 --- a/gcc-4.9/gcc/po/sv.po +++ b/gcc-4.9/gcc/po/sv.po @@ -16,7 +16,7 @@ msgstr "" "Project-Id-Version: gcc 4.9-b20140202\n" "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n" "POT-Creation-Date: 2014-02-02 17:35+0000\n" -"PO-Revision-Date: 2014-03-30 20:23+0200\n" +"PO-Revision-Date: 2014-04-11 20:56+0200\n" "Last-Translator: Göran Uddeborg \n" "Language-Team: Swedish \n" "Language: sv\n" @@ -1493,7 +1493,7 @@ msgstr "attributen för optimeringsnivåer stämmer inte" #: cif-code.def:125 msgid "callee refers to comdat-local symbols" -msgstr "den anropade referarar till comdat-lokala symboler" +msgstr "den anropade refererar till comdat-lokala symboler" #. The remainder are real diagnostic types. #: diagnostic.def:33 @@ -6065,7 +6065,7 @@ msgstr "Varna för missbruk av pragman" #: c-family/c.opt:653 msgid "Warn about __TIME__, __DATE__ and __TIMESTAMP__ usage" -msgstr "Warn för använding av __TIME__, __DATE__ och __TIMESTAMP__" +msgstr "Varna för användning av __TIME__, __DATE__ och __TIMESTAMP__" #: c-family/c.opt:657 msgid "Warn if a property for an Objective-C object has no assign semantics specified" @@ -12220,7 +12220,7 @@ msgstr "-dumpdir \tAnge katalognamn att användas för dumpar" #: common.opt:811 msgid "Aggressively optimize loops using language constraints" -msgstr "Optimera aggresivt slingor med användning av språkbegränsningar" +msgstr "Optimera aggressivt slingor med användning av språkbegränsningar" #: common.opt:815 msgid "Align the start of functions" @@ -13449,7 +13449,7 @@ msgstr "okänd kostnadsmodell för vektorisering %qs" #: common.opt:2332 msgid "Enables the dynamic vectorizer cost model. Preserved for backward compatibility." -msgstr "Aktivera den dynamiska kostnadsmodellen för vekoriseraren. Bevarad för bakåtkompatibilitet." +msgstr "Aktivera den dynamiska kostnadsmodellen för vektoriseraren. Bevarad för bakåtkompatibilitet." #: common.opt:2336 msgid "Enables the unlimited vectorizer cost model. Preserved for backward compatibility." @@ -19151,7 +19151,7 @@ msgstr "längden stämmer inte i uttryck" #: c/c-array-notation.c:721 cp/cp-array-notation.c:610 #, gcc-internal-format msgid "rank mismatch between %qE and %qE" -msgstr "ordingen stämmer inte mellan %qE och %qE" +msgstr "ordningen stämmer inte mellan %qE och %qE" #. Here the original expression is printed as a "heads-up" #. to the programmer. This is because since there is no @@ -25782,7 +25782,7 @@ msgstr "felaktig DISPOSE-konstruktion: %d" msgid "too much stack space to dispose of: %d" msgstr "för mycket stackutrymme att göra av med: %d" -# Förmodligen en felstavning i orginalet, men tills jag vet säkert +# Förmodligen en felstavning i originalet, men tills jag vet säkert # behåller jag den #: config/v850/v850.c:2788 #, gcc-internal-format, gfc-internal-format @@ -28130,7 +28130,7 @@ msgstr "den andra matchen är här" #: c/c-parser.c:6884 #, gcc-internal-format msgid "%<_Generic%> selector of type %qT is not compatible with any association" -msgstr "%<_Generic%>-väljare av typ %qT är inte kompatiblem med någon association" +msgstr "%<_Generic%>-väljare av typ %qT är inte kompatibel med någon association" #: c/c-parser.c:7039 c/c-parser.c:7519 c/c-parser.c:7538 #, gcc-internal-format @@ -28185,7 +28185,7 @@ msgstr "-fcilkplus måste vara aktiverat för att använda %<_Cilk_spawn%>" #: c/c-parser.c:7505 cp/parser.c:5807 #, gcc-internal-format msgid "consecutive %<_Cilk_spawn%> keywords are not permitted" -msgstr "konsektiva %<_Cilk_spawn%>-nyckelord är inte tillåtet" +msgstr "konsekutiva %<_Cilk_spawn%>-nyckelord är inte tillåtet" #: c/c-parser.c:7573 #, gcc-internal-format @@ -31055,7 +31055,7 @@ msgstr "%qD kan inte vara en skalär när %qD inte är det" #: cp/cp-array-notation.c:849 cp/cp-array-notation.c:855 #, gcc-internal-format msgid "rank mismatch with controlling expression of parent if-statement" -msgstr "ordingen stämmer inte med det styrande uttrycket i förälder-if-satsen" +msgstr "ordningen stämmer inte med det styrande uttrycket i förälder-if-satsen" #: cp/cp-array-notation.c:1250 #, gcc-internal-format @@ -31090,7 +31090,7 @@ msgstr "startindex och längdfält är nödvändiga för att använda vektornota #: cp/cp-array-notation.c:1422 #, gcc-internal-format msgid "array notation cannot be used with function type" -msgstr "vektornotation kan inte användas användas med en funktionstyp" +msgstr "vektornotation kan inte användas med en funktionstyp" #: cp/cp-array-notation.c:1432 #, gcc-internal-format @@ -31100,7 +31100,7 @@ msgstr "ordningen på en vektornotations trippels startindex är inte noll" #: cp/cp-array-notation.c:1438 #, gcc-internal-format msgid "rank of an array notation triplet%'s length is not zero" -msgstr "ordingen på en vektornotations trippels längd är inte noll" +msgstr "ordningen på en vektornotations trippels längd är inte noll" #: cp/cp-array-notation.c:1443 #, gcc-internal-format @@ -31450,7 +31450,7 @@ msgstr "standardtypkonvertering kan inte härleda mallargumentet för %qD" #: cp/cvt.c:1659 #, gcc-internal-format msgid "ambiguous default type conversion from %qT" -msgstr "tvetydig standartypkonvertering från %qT" +msgstr "tvetydig standardtypkonvertering från %qT" #: cp/cvt.c:1661 #, gcc-internal-format @@ -33747,7 +33747,7 @@ msgstr "%qD är redan definierad i klassen %qT" #: cp/decl.c:14531 cp/decl2.c:4673 #, gcc-internal-format msgid "use of %qD before deduction of %" -msgstr "använding av %qD före härledning av %" +msgstr "användning av %qD före härledning av %" #: cp/decl2.c:322 #, gcc-internal-format @@ -36027,7 +36027,7 @@ msgstr "användning av % i lambdaparameterdeklarationer är endast tillg #: cp/parser.c:14516 #, gcc-internal-format msgid "use of % in parameter declaration only available with -std=c++1y or -std=gnu++1y" -msgstr "använding av % i parameterdeklarationer är endast tillgängligt med -std=c++1y eller -std=gnu++1y" +msgstr "användning av % i parameterdeklarationer är endast tillgängligt med -std=c++1y eller -std=gnu++1y" #: cp/parser.c:14521 #, gcc-internal-format @@ -37288,7 +37288,7 @@ msgstr " men %d behövs" #: cp/pt.c:4861 #, gcc-internal-format msgid "template arguments to %qD do not match original template %qD" -msgstr "mallargument till %qD stämmer inte med orginalmallen %qD" +msgstr "mallargument till %qD stämmer inte med originalmallen %qD" #: cp/pt.c:4865 #, gcc-internal-format @@ -38326,7 +38326,7 @@ msgstr "det går inte att applicera % på destrueraren %<~%T%>" #: cp/semantics.c:3800 #, gcc-internal-format msgid "second operand of % is neither a single identifier nor a sequence of member accesses and array references" -msgstr "andra operanden till % är varken en ensam idientifierare eller en sekvens av medlemsåtkomster och vektorreferenser" +msgstr "andra operanden till % är varken en ensam identifierare eller en sekvens av medlemsåtkomster och vektorreferenser" #: cp/semantics.c:3808 #, gcc-internal-format @@ -48120,7 +48120,7 @@ msgstr "Variabeln ”%s” vid %L av TYPE(C_PTR) eller TYPE(C_FUNPTR) får inte #: fortran/resolve.c:13229 #, gcc-internal-format, gfc-internal-format msgid "Variable '%s' at %L with coarray component shall be a nonpointer, nonallocatable scalar, which is not a coarray" -msgstr "Variabeln ”%s” vid %L med co-vektorkomponent skall vara en skalär som inte är en pekare eller allokerbar och inte en co-vaktor" +msgstr "Variabeln ”%s” vid %L med co-vektorkomponent skall vara en skalär som inte är en pekare eller allokerbar och inte en co-vektor" #: fortran/resolve.c:13244 #, gcc-internal-format, gfc-internal-format @@ -49576,12 +49576,12 @@ msgstr "tidigare definition här" #: lto/lto-symtab.c:404 #, gcc-internal-format msgid "type of %qD does not match original declaration" -msgstr "typen på %qD stämmer inte med orginaldeklarationen" +msgstr "typen på %qD stämmer inte med originaldeklarationen" #: lto/lto-symtab.c:412 #, gcc-internal-format msgid "alignment of %qD is bigger than original declaration" -msgstr "justering av %qD är större än orginaldeklarationen" +msgstr "justering av %qD är större än originaldeklarationen" #: lto/lto-symtab.c:418 lto/lto-symtab.c:517 #, gcc-internal-format diff --git a/gcc-4.9/gcc/testsuite/ChangeLog b/gcc-4.9/gcc/testsuite/ChangeLog index 4c09a1e05..104703076 100644 --- a/gcc-4.9/gcc/testsuite/ChangeLog +++ b/gcc-4.9/gcc/testsuite/ChangeLog @@ -1,3 +1,297 @@ +2014-05-14 Matthias Klose + + PR driver/61106 + * gcc-dg/unused-8a.c: Remove. + +2014-05-13 Peter Bergner + + * lib/target-support.exp (check_dfp_hw_available): New function. + (is-effective-target): Check $arg for dfp_hw. + (is-effective-target-keyword): Likewise. + * gcc.target/powerpc/pack03.c: (dg-require-effective-target): + Change target to dfp_hw. + +2014-05-13 Jeff Law + + Backports from mainline + + 2014-05-08 Jeff Law + + PR tree-optimization/61009 + * g++.dg/tree-ssa/pr61009.C: New test. + + 2014-04-23 Jeff Law + + PR tree-optimization/60902 + * gcc.target/i386/pr60902.c: New test. + +2014-05-13 Jakub Jelinek + + PR target/61060 + * gcc.dg/pr61060.c: New test. + +2014-05-12 Senthil Kumar Selvaraj + + Backport from mainline + 2014-05-12 Senthil Kumar Selvaraj + + PR target/60991 + * gcc.target/avr/pr60991.c: New testcase. + +2014-05-10 Jerry DeLisle + + Backport from trunk. + PR libfortran/61049 + * gfortran.dg/list_read_13.f: New test. + +2014-05-09 Georg-Johann Lay + + Backport from 2014-05-09 trunk r210267 + + PR target/61055 + * gcc.target/avr/torture/pr61055.c: New test. + +2014-05-08 Matthias Klose + + PR driver/61106 + * gcc-dg/unused-8a.c: New. + * gcc-dg/unused-8b.c: Likewise. + +2014-05-07 Paolo Carlini + + PR c++/61083 + * g++.dg/cpp0x/sfinae50.C: New. + +2014-05-07 Richard Biener + + PR tree-optimization/57864 + * gcc.dg/torture/pr57864.c: New testcase. + +2014-05-06 Paolo Carlini + + PR c++/60999 + * g++.dg/cpp0x/nsdmi-template9.C: New. + * g++.dg/cpp0x/nsdmi-template10.C: Likewise. + +2014-05-04 Jan Hubicka + + PR ipa/60965 + * g++.dg/ipa/devirt-31.C: New testcase. + * g++.dg/ipa/devirt-11.C: Adjust testcase. + +2014-05-04 Peter Bergner + + * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float. + (dg-require-effective-target): Change target to powerpc_fprs. + * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp. + (dg-require-effective-target): Change target to dfprt. + +2014-05-02 Bill Schmidt + + PR tree-optimization/60930 + * gcc.dg/torture/pr60930.c: New test. + +2014-04-30 Michael Meissner + + Back port from mainline + 2014-04-24 Michael Meissner + + * gcc.target/powerpc/pack01.c: New test to test the new pack and + unpack builtin functionss for 128-bit types. + * gcc.target/powerpc/pack02.c: Likewise. + * gcc.target/powerpc/pack03.c: Likewise. + * gcc.target/powerpc/extend-divide-1.c: New test to test extended + divide builtin functionss. + * gcc.target/powerpc/extend-divide-2.c: Likewise. + * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin + functions. + * gcc.target/powerpc/bcd-2.c: Likewise. + * gcc.target/powerpc/bcd-3.c: Likewise. + * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP + builtin functionss. + * gcc.target/powerpc/dfp-builtin-2.c: Likewise. + +2014-04-29 Pat Haugen + + Backport from mainline + 2014-04-17 Pat Haugen + + * gcc.target/powerpc/ti_math1.c: New. + * gcc.target/powerpc/ti_math2.c: New. + +2014-04-29 Jakub Jelinek + + PR tree-optimization/60971 + * c-c++-common/turtore/pr60971.c: New test. + +2014-04-26 Uros Bizjak + + * gcc.dg/tree-ssa/alias-30.c (dg-options): Dump only fre1 details. + * gcc.dg/vect/pr60505.c: Cleanup vect tree dump. + * g++.dg/ipa/devirt-27.C (dg-options): Remove -fdump-ipa-devirt. + +2014-04-25 Uros Bizjak + + * c-c++-common/gomp/pr60823-2.c: Require effective target + vect_simd_clones. + +2014-04-25 Jakub Jelinek + + PR tree-optimization/60960 + * gcc.c-torture/execute/pr60960.c: New test. + +2014-04-25 Eric Botcazou + + * gcc.c-torture/execute/20140425-1.c: New test. + +2014-04-25 Richard Biener + + PR ipa/60912 + * g++.dg/opt/pr60912.C: New testcase. + +2014-04-25 Richard Biener + + PR ipa/60911 + * gcc.dg/lto/pr60911_0.c: New testcase. + +2014-04-24 Jakub Jelinek + + * c-c++-common/gomp/atomic-16.c: Remove all dg-error directives. + Replace load with read and store with write. + +2014-04-23 Uros Bizjak + + Backport from mainline + 2014-04-21 Uros Bizjak + + PR target/60909 + * gcc.target/i386/pr60909-1.c: New test. + * gcc.target/i386/pr60909-2.c: Ditto. + +2014-04-23 Richard Biener + + PR tree-optimization/60903 + * gcc.dg/torture/pr60903.c: New testcase. + +2014-04-23 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR lto/60720 + * gcc.dg/lto/pr60720_0.c: New testcase. + * gcc.dg/lto/pr60720_1.c: Likewise. + +2014-04-23 Richard Biener + + PR middle-end/60895 + * g++.dg/torture/pr60895.C: New testcase. + +2014-04-23 Richard Biener + + PR middle-end/60891 + * gcc.dg/torture/pr60891.c: New testcase. + +2014-04-22 Michael Meissner + + Backport from mainline + 2014-04-21 Michael Meissner + + PR target/60735 + * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does + not cause errors if -mspe. + +2014-04-22 Tobias Burnus + + Backport from mainline + 2014-04-11 Tobias Burnus + + PR fortran/58880 + PR fortran/60495 + * gfortran.dg/finalize_25.f90: New. + +2014-04-22 H.J. Lu + + Backport from mainline + 2014-04-22 H.J. Lu + + * gcc.target/i386/pr60868.c: New testcase. + +2014-04-22 Jakub Jelinek + + PR c/59073 + * c-c++-common/gomp/pr59073.c: New test. + +2014-04-22 Bill Schmidt + + * gcc.dg/vmx/merge-vsx.c: Add V4SI and V4SF tests. + * gcc.dg/vmx/merge-vsx-be-order.c: Likewise. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR middle-end/55022 + * gcc.dg/graphite/pr55022.c: New testcase. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR middle-end/60849 + * g++.dg/opt/pr60849.C: New testcase. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR tree-optimization/60841 + * gcc.dg/vect/pr60841.c: New testcase. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR tree-optimization/60836 + * g++.dg/vect/pr60836.cc: New testcase. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + Marc Glisse + + PR c/60819 + * gcc.target/i386/vec-may_alias.c: New testcase. + +2014-04-22 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR tree-optimization/59817 + PR tree-optimization/60453 + * gfortran.dg/graphite/pr59817.f: New testcase. + * gcc.dg/graphite/pr59817-1.c: Likewise. + * gcc.dg/graphite/pr59817-2.c: Likewise. + +2014-04-22 Jakub Jelinek + + PR tree-optimization/60823 + * c-c++-common/gomp/pr60823-1.c: New test. + * c-c++-common/gomp/pr60823-2.c: New test. + * c-c++-common/gomp/pr60823-3.c: New test. + + Backported from mainline + 2014-04-16 Jakub Jelinek + + PR tree-optimization/60844 + * gcc.dg/pr60844.c: New test. + 2014-04-22 Release Manager * GCC 4.9.0 released. @@ -51,7 +345,7 @@ 2014-04-12 Jerry DeLisle PR libfortran/60810 - gfortran.dg/arrayio_13.f90: New test. + * gfortran.dg/arrayio_13.f90: New test. 2014-04-11 Steve Ellcey Jakub Jelinek @@ -135,8 +429,7 @@ 2014-04-08 Jason Merrill - * lib/gcc-dg.exp (dg-build-dso): Reset dg-do-what-default to - compile. + * lib/gcc-dg.exp (dg-build-dso): Reset dg-do-what-default to compile. 2014-04-08 Andreas Krebbel @@ -256,10 +549,10 @@ 2014-04-04 Martin Jambor PR ipa/60640 - * g++.dg/ipa/pr60640-1.C: New test. - * g++.dg/ipa/pr60640-2.C: Likewise. - * g++.dg/ipa/pr60640-3.C: Likewise. - * g++.dg/ipa/pr60640-4.C: Likewise. + * g++.dg/ipa/pr60640-1.C: New test. + * g++.dg/ipa/pr60640-2.C: Likewise. + * g++.dg/ipa/pr60640-3.C: Likewise. + * g++.dg/ipa/pr60640-4.C: Likewise. 2014-04-04 Jeff Law @@ -371,7 +664,7 @@ 2014-04-01 Fabien Chêne - * g++.dg/init/ctor4.C: Adjust. + * g++.dg/init/ctor4.C: Adjust. * g++.dg/init/ctor4-1.C: New. * g++.dg/cpp0x/defaulted2.C: Adjust. @@ -459,8 +752,8 @@ 2014-03-27 Jeff Law - PR target/60648 - * g++.dg/pr60648.C: New test. + PR target/60648 + * g++.dg/pr60648.C: New test. 2014-03-28 Adam Butcher @@ -493,14 +786,13 @@ 2014-03-28 Andreas Krebbel - * gcc.dg/tree-ssa/ssa-dom-thread-4.c: Remove s390 special - option. + * gcc.dg/tree-ssa/ssa-dom-thread-4.c: Remove s390 special option. * lib/target-supports.exp: Return true for s390 - in check_effective_logical_op_short_circuit. + in check_effective_logical_op_short_circuit. 2014-03-28 Kirill Yukhin - * gcc.target/i386/avx512f-vshuff32x4-2.c: Fix initialization + * gcc.target/i386/avx512f-vshuff32x4-2.c: Fix initialization of second source operand. * gcc.target/i386/avx512f-vshuff64x2-2.c: Ditto. * gcc.target/i386/avx512f-vshufi32x4-2.c: Ditto. @@ -635,8 +927,8 @@ 2014-03-24 Marek Polacek - * c-c++-common/ubsan/div-by-zero-4.c: Don't include limits.h. Define - INT_MIN. + * c-c++-common/ubsan/div-by-zero-4.c: Don't include limits.h. + Define INT_MIN. * c-c++-common/ubsan/overflow-1.c: Check for unwanted output. * c-c++-common/ubsan/overflow-add-1.c: Likewise. * c-c++-common/ubsan/overflow-mul-1.c: Likewise. @@ -721,8 +1013,7 @@ 2014-03-21 Tobias Burnus PR fortran/60599 - * lib/gcc-dg.exp (scan-module): Uncompress .mod files for - reading. + * lib/gcc-dg.exp (scan-module): Uncompress .mod files for reading. 2014-03-20 Jakub Jelinek @@ -1540,8 +1831,7 @@ 2014-02-19 Paul Pluzhnikov - * gcc.dg/vect/no-vfa-vect-depend-2.c (main1): Fix buffer - overflow. + * gcc.dg/vect/no-vfa-vect-depend-2.c (main1): Fix buffer overflow. 2014-02-19 Jakub Jelinek @@ -1850,8 +2140,7 @@ 2014-02-10 Jakub Jelinek - * gcc.dg/vect/pr59984.c: Require effective target - vect_simd_clones. + * gcc.dg/vect/pr59984.c: Require effective target vect_simd_clones. 2014-02-09 Paul Thomas @@ -3098,8 +3387,8 @@ * gfortran.dg/vect/fast-math-mgrid-resid.f: Change -fdump-tree-optimized to -fdump-tree-pcom-details in dg-options and cleanup-tree-dump from optimized to pcom. Remove scan-tree-dump-times - for vect_\[^\\n\]*\\+, add scan-tree-dump-times for no suitable chains and - Executing predictive commoning without unrolling. + for vect_\[^\\n\]*\\+, add scan-tree-dump-times for no suitable + chains and Executing predictive commoning without unrolling. 2014-01-14 Kirill Yukhin diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/gomp/atomic-16.c b/gcc-4.9/gcc/testsuite/c-c++-common/gomp/atomic-16.c index 87fbaa233..9332396ea 100644 --- a/gcc-4.9/gcc/testsuite/c-c++-common/gomp/atomic-16.c +++ b/gcc-4.9/gcc/testsuite/c-c++-common/gomp/atomic-16.c @@ -7,28 +7,28 @@ void foo () { int v; - #pragma omp atomic seq_cst load /* { dg-error "expected end of line" } */ - v = x; /* { dg-error "invalid form" } */ - #pragma omp atomic seq_cst, load /* { dg-error "expected end of line" } */ - v = x; /* { dg-error "invalid form" } */ - #pragma omp atomic seq_cst store /* { dg-error "expected end of line" } */ - x = v; /* { dg-error "invalid form" } */ - #pragma omp atomic seq_cst ,store /* { dg-error "expected end of line" } */ - x = v; /* { dg-error "invalid form" } */ - #pragma omp atomic seq_cst update /* { dg-error "expected end of line" } */ + #pragma omp atomic seq_cst read + v = x; + #pragma omp atomic seq_cst, read + v = x; + #pragma omp atomic seq_cst write + x = v; + #pragma omp atomic seq_cst ,write + x = v; + #pragma omp atomic seq_cst update x += v; - #pragma omp atomic seq_cst , update /* { dg-error "expected end of line" } */ + #pragma omp atomic seq_cst , update x += v; - #pragma omp atomic seq_cst capture /* { dg-error "expected end of line" } */ - v = x += 2; /* { dg-error "invalid form" } */ - #pragma omp atomic seq_cst, capture /* { dg-error "expected end of line" } */ - v = x += 2; /* { dg-error "invalid form" } */ - #pragma omp atomic load , seq_cst /* { dg-error "expected end of line" } */ - v = x; /* { dg-error "invalid form" } */ - #pragma omp atomic store ,seq_cst /* { dg-error "expected end of line" } */ - x = v; /* { dg-error "invalid form" } */ - #pragma omp atomic update, seq_cst /* { dg-error "expected end of line" } */ + #pragma omp atomic seq_cst capture + v = x += 2; + #pragma omp atomic seq_cst, capture + v = x += 2; + #pragma omp atomic read , seq_cst + v = x; + #pragma omp atomic write ,seq_cst + x = v; + #pragma omp atomic update, seq_cst x += v; - #pragma omp atomic capture, seq_cst /* { dg-error "expected end of line" } */ + #pragma omp atomic capture, seq_cst v = x += 2; } diff --git a/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-11.C b/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-11.C index d30d56cff..ca8ea4cc2 100644 --- a/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-11.C +++ b/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-11.C @@ -45,5 +45,5 @@ bar () /* While inlining function called once we should devirtualize a new call to fn2 and two to fn3. While doing so the new symbol for fn2 needs to be introduced. */ -/* { dg-final { scan-ipa-dump-times "Discovered a virtual call to a known target" 3 "inline" } } */ +/* { dg-final { scan-ipa-dump-times "Discovered a virtual call to a known target" 1 "inline" } } */ /* { dg-final { cleanup-ipa-dump "inline" } } */ diff --git a/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-27.C b/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-27.C index 1dcf76cc3..749f40af1 100644 --- a/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-27.C +++ b/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-27.C @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -fdump-ipa-devirt -fdump-tree-optimized" } */ +/* { dg-options "-O3 -fdump-tree-optimized" } */ struct A { int a; diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c b/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c index addf12840..7ef830d19 100644 --- a/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c +++ b/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/alias-30.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -fdump-tree-fre-details" } */ +/* { dg-options "-O -fdump-tree-fre1-details" } */ extern int posix_memalign(void **memptr, __SIZE_TYPE__ alignment, __SIZE_TYPE__ size); diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr60505.c b/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr60505.c index 694051320..70e2ec06f 100644 --- a/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr60505.c +++ b/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr60505.c @@ -10,3 +10,5 @@ void foo(char *in, char *out, int num) out[i] = (ovec[i] = in[i]); out[num] = ovec[num/2]; } + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c b/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c index 440ac9a00..56e0b0e6c 100644 --- a/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c +++ b/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c @@ -21,10 +21,19 @@ static void test() vector long long vlb = {0,1}; vector double vda = {-2.0,-1.0}; vector double vdb = {0.0,1.0}; + vector unsigned int vuia = {0,1,2,3}; + vector unsigned int vuib = {4,5,6,7}; + vector signed int vsia = {-4,-3,-2,-1}; + vector signed int vsib = {0,1,2,3}; + vector float vfa = {-4.0,-3.0,-2.0,-1.0}; + vector float vfb = {0.0,1.0,2.0,3.0}; /* Result vectors. */ vector long long vlh, vll; vector double vdh, vdl; + vector unsigned int vuih, vuil; + vector signed int vsih, vsil; + vector float vfh, vfl; /* Expected result vectors. */ #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ @@ -32,20 +41,44 @@ static void test() vector long long vlrl = {0,-2}; vector double vdrh = {1.0,-1.0}; vector double vdrl = {0.0,-2.0}; + vector unsigned int vuirh = {6,2,7,3}; + vector unsigned int vuirl = {4,0,5,1}; + vector signed int vsirh = {2,-2,3,-1}; + vector signed int vsirl = {0,-4,1,-3}; + vector float vfrh = {2.0,-2.0,3.0,-1.0}; + vector float vfrl = {0.0,-4.0,1.0,-3.0}; #else vector long long vlrh = {-2,0}; vector long long vlrl = {-1,1}; vector double vdrh = {-2.0,0.0}; vector double vdrl = {-1.0,1.0}; + vector unsigned int vuirh = {0,4,1,5}; + vector unsigned int vuirl = {2,6,3,7}; + vector signed int vsirh = {-4,0,-3,1}; + vector signed int vsirl = {-2,2,-1,3}; + vector float vfrh = {-4.0,0.0,-3.0,1.0}; + vector float vfrl = {-2.0,2.0,-1.0,3.0}; #endif vlh = vec_mergeh (vla, vlb); vll = vec_mergel (vla, vlb); vdh = vec_mergeh (vda, vdb); vdl = vec_mergel (vda, vdb); + vuih = vec_mergeh (vuia, vuib); + vuil = vec_mergel (vuia, vuib); + vsih = vec_mergeh (vsia, vsib); + vsil = vec_mergel (vsia, vsib); + vfh = vec_mergeh (vfa, vfb ); + vfl = vec_mergel (vfa, vfb ); check (vec_long_long_eq (vlh, vlrh), "vlh"); check (vec_long_long_eq (vll, vlrl), "vll"); check (vec_double_eq (vdh, vdrh), "vdh" ); check (vec_double_eq (vdl, vdrl), "vdl" ); + check (vec_all_eq (vuih, vuirh), "vuih"); + check (vec_all_eq (vuil, vuirl), "vuil"); + check (vec_all_eq (vsih, vsirh), "vsih"); + check (vec_all_eq (vsil, vsirl), "vsil"); + check (vec_all_eq (vfh, vfrh), "vfh"); + check (vec_all_eq (vfl, vfrl), "vfl"); } diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx.c b/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx.c index 851f35bd3..40693e95b 100644 --- a/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx.c +++ b/gcc-4.9/gcc/testsuite/gcc.dg/vmx/merge-vsx.c @@ -21,24 +21,51 @@ static void test() vector long long vlb = {0,1}; vector double vda = {-2.0,-1.0}; vector double vdb = {0.0,1.0}; + vector unsigned int vuia = {0,1,2,3}; + vector unsigned int vuib = {4,5,6,7}; + vector signed int vsia = {-4,-3,-2,-1}; + vector signed int vsib = {0,1,2,3}; + vector float vfa = {-4.0,-3.0,-2.0,-1.0}; + vector float vfb = {0.0,1.0,2.0,3.0}; /* Result vectors. */ vector long long vlh, vll; vector double vdh, vdl; + vector unsigned int vuih, vuil; + vector signed int vsih, vsil; + vector float vfh, vfl; /* Expected result vectors. */ vector long long vlrh = {-2,0}; vector long long vlrl = {-1,1}; vector double vdrh = {-2.0,0.0}; vector double vdrl = {-1.0,1.0}; + vector unsigned int vuirh = {0,4,1,5}; + vector unsigned int vuirl = {2,6,3,7}; + vector signed int vsirh = {-4,0,-3,1}; + vector signed int vsirl = {-2,2,-1,3}; + vector float vfrh = {-4.0,0.0,-3.0,1.0}; + vector float vfrl = {-2.0,2.0,-1.0,3.0}; vlh = vec_mergeh (vla, vlb); vll = vec_mergel (vla, vlb); vdh = vec_mergeh (vda, vdb); vdl = vec_mergel (vda, vdb); + vuih = vec_mergeh (vuia, vuib); + vuil = vec_mergel (vuia, vuib); + vsih = vec_mergeh (vsia, vsib); + vsil = vec_mergel (vsia, vsib); + vfh = vec_mergeh (vfa, vfb ); + vfl = vec_mergel (vfa, vfb ); check (vec_long_long_eq (vlh, vlrh), "vlh"); check (vec_long_long_eq (vll, vlrl), "vll"); check (vec_double_eq (vdh, vdrh), "vdh" ); check (vec_double_eq (vdl, vdrl), "vdl" ); + check (vec_all_eq (vuih, vuirh), "vuih"); + check (vec_all_eq (vuil, vuirl), "vuil"); + check (vec_all_eq (vsih, vsirh), "vsih"); + check (vec_all_eq (vsil, vsirl), "vsil"); + check (vec_all_eq (vfh, vfrh), "vfh"); + check (vec_all_eq (vfl, vfrl), "vfl"); } diff --git a/gcc-4.9/gcc/testsuite/lib/target-supports.exp b/gcc-4.9/gcc/testsuite/lib/target-supports.exp index 57b10d0a8..7d296d902 100644 --- a/gcc-4.9/gcc/testsuite/lib/target-supports.exp +++ b/gcc-4.9/gcc/testsuite/lib/target-supports.exp @@ -1956,6 +1956,32 @@ proc check_effective_target_dfprt { } { }] } +# Return 1 if the target supports executing DFP hardware instructions, +# 0 otherwise. Cache the result. + +proc check_dfp_hw_available { } { + return [check_cached_effective_target dfp_hw_available { + # For now, disable on Darwin + if { [istarget powerpc-*-eabi] || [istarget powerpc*-*-eabispe] || [istarget *-*-darwin*]} { + expr 0 + } else { + check_runtime_nocache dfp_hw_available { + volatile _Decimal64 r; + volatile _Decimal64 a = 4.0DD; + volatile _Decimal64 b = 2.0DD; + int main() + { + asm volatile ("dadd %0,%1,%2" : "=d" (r) : "d" (a), "d" (b)); + asm volatile ("dsub %0,%1,%2" : "=d" (r) : "d" (a), "d" (b)); + asm volatile ("dmul %0,%1,%2" : "=d" (r) : "d" (a), "d" (b)); + asm volatile ("ddiv %0,%1,%2" : "=d" (r) : "d" (a), "d" (b)); + return 0; + } + } "-mcpu=power6 -mhard-float" + } + }] +} + # Return 1 if the target supports compiling and assembling UCN, 0 otherwise. proc check_effective_target_ucn_nocache { } { @@ -4919,6 +4945,7 @@ proc is-effective-target { arg } { "vsx_hw" { set selected [check_vsx_hw_available] } "p8vector_hw" { set selected [check_p8vector_hw_available] } "ppc_recip_hw" { set selected [check_ppc_recip_hw_available] } + "dfp_hw" { set selected [check_dfp_hw_available] } "named_sections" { set selected [check_named_sections_available] } "gc_sections" { set selected [check_gc_sections_available] } "cxa_atexit" { set selected [check_cxa_atexit_available] } @@ -4941,6 +4968,7 @@ proc is-effective-target-keyword { arg } { "vsx_hw" { return 1 } "p8vector_hw" { return 1 } "ppc_recip_hw" { return 1 } + "dfp_hw" { return 1 } "named_sections" { return 1 } "gc_sections" { return 1 } "cxa_atexit" { return 1 } diff --git a/gcc-4.9/gcc/tree-dfa.c b/gcc-4.9/gcc/tree-dfa.c index fcf8d80fd..a1f275874 100644 --- a/gcc-4.9/gcc/tree-dfa.c +++ b/gcc-4.9/gcc/tree-dfa.c @@ -343,7 +343,7 @@ set_ssa_default_def (struct function *fn, tree var, tree def) { loc = htab_find_slot_with_hash (DEFAULT_DEFS (fn), &in, DECL_UID (var), NO_INSERT); - if (*loc) + if (loc) { SSA_NAME_IS_DEFAULT_DEF (*(tree *)loc) = false; htab_clear_slot (DEFAULT_DEFS (fn), loc); diff --git a/gcc-4.9/gcc/tree-inline.c b/gcc-4.9/gcc/tree-inline.c index 429324138..04d099f61 100644 --- a/gcc-4.9/gcc/tree-inline.c +++ b/gcc-4.9/gcc/tree-inline.c @@ -1485,6 +1485,11 @@ remap_gimple_stmt (gimple stmt, copy_body_data *id) /* Create a new deep copy of the statement. */ copy = gimple_copy (stmt); + /* Clear flags that need revisiting. */ + if (is_gimple_call (copy) + && gimple_call_tail_p (copy)) + gimple_call_set_tail (copy, false); + /* Remap the region numbers for __builtin_eh_{pointer,filter}, RESX and EH_DISPATCH. */ if (id->eh_map) @@ -3119,7 +3124,8 @@ declare_return_variable (copy_body_data *id, tree return_slot, tree modify_dest, { var = return_slot; gcc_assert (TREE_CODE (var) != SSA_NAME); - TREE_ADDRESSABLE (var) |= TREE_ADDRESSABLE (result); + if (TREE_ADDRESSABLE (result)) + mark_addressable (var); } if ((TREE_CODE (TREE_TYPE (result)) == COMPLEX_TYPE || TREE_CODE (TREE_TYPE (result)) == VECTOR_TYPE) diff --git a/gcc-4.9/gcc/tree-nested.c b/gcc-4.9/gcc/tree-nested.c index df6923f76..9c175de4e 100644 --- a/gcc-4.9/gcc/tree-nested.c +++ b/gcc-4.9/gcc/tree-nested.c @@ -1082,6 +1082,11 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) need_stmts = true; goto do_decl_clause; + case OMP_CLAUSE_LINEAR: + if (OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause)) + need_stmts = true; + goto do_decl_clause; + case OMP_CLAUSE_PRIVATE: case OMP_CLAUSE_FIRSTPRIVATE: case OMP_CLAUSE_COPYPRIVATE: @@ -1157,6 +1162,12 @@ convert_nonlocal_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause)); break; + case OMP_CLAUSE_LINEAR: + walk_body (convert_nonlocal_reference_stmt, + convert_nonlocal_reference_op, info, + &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause)); + break; + default: break; } @@ -1605,6 +1616,11 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) need_stmts = true; goto do_decl_clause; + case OMP_CLAUSE_LINEAR: + if (OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause)) + need_stmts = true; + goto do_decl_clause; + case OMP_CLAUSE_PRIVATE: case OMP_CLAUSE_FIRSTPRIVATE: case OMP_CLAUSE_COPYPRIVATE: @@ -1685,6 +1701,12 @@ convert_local_omp_clauses (tree *pclauses, struct walk_stmt_info *wi) &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause)); break; + case OMP_CLAUSE_LINEAR: + walk_body (convert_local_reference_stmt, + convert_local_reference_op, info, + &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause)); + break; + default: break; } diff --git a/gcc-4.9/gcc/tree-ssa-loop-im.c b/gcc-4.9/gcc/tree-ssa-loop-im.c index c75f25749..1b4019041 100644 --- a/gcc-4.9/gcc/tree-ssa-loop-im.c +++ b/gcc-4.9/gcc/tree-ssa-loop-im.c @@ -1544,15 +1544,6 @@ analyze_memory_references (void) struct loop *loop, *outer; unsigned i, n; -#if 0 - /* Initialize bb_loop_postorder with a mapping from loop->num to - its postorder index. */ - i = 0; - bb_loop_postorder = XNEWVEC (unsigned, number_of_loops (cfun)); - FOR_EACH_LOOP (loop, LI_FROM_INNERMOST) - bb_loop_postorder[loop->num] = i++; -#endif - /* Collect all basic-blocks in loops and sort them after their loops postorder. */ i = 0; @@ -1807,6 +1798,7 @@ execute_sm_if_changed (edge ex, tree mem, tree tmp_var, tree flag) gimple_stmt_iterator gsi; gimple stmt; struct prev_flag_edges *prev_edges = (struct prev_flag_edges *) ex->aux; + bool irr = ex->flags & EDGE_IRREDUCIBLE_LOOP; /* ?? Insert store after previous store if applicable. See note below. */ @@ -1821,8 +1813,9 @@ execute_sm_if_changed (edge ex, tree mem, tree tmp_var, tree flag) old_dest = ex->dest; new_bb = split_edge (ex); then_bb = create_empty_bb (new_bb); - if (current_loops && new_bb->loop_father) - add_bb_to_loop (then_bb, new_bb->loop_father); + if (irr) + then_bb->flags = BB_IRREDUCIBLE_LOOP; + add_bb_to_loop (then_bb, new_bb->loop_father); gsi = gsi_start_bb (new_bb); stmt = gimple_build_cond (NE_EXPR, flag, boolean_false_node, @@ -1834,9 +1827,12 @@ execute_sm_if_changed (edge ex, tree mem, tree tmp_var, tree flag) stmt = gimple_build_assign (unshare_expr (mem), tmp_var); gsi_insert_after (&gsi, stmt, GSI_CONTINUE_LINKING); - make_edge (new_bb, then_bb, EDGE_TRUE_VALUE); - make_edge (new_bb, old_dest, EDGE_FALSE_VALUE); - then_old_edge = make_edge (then_bb, old_dest, EDGE_FALLTHRU); + make_edge (new_bb, then_bb, + EDGE_TRUE_VALUE | (irr ? EDGE_IRREDUCIBLE_LOOP : 0)); + make_edge (new_bb, old_dest, + EDGE_FALSE_VALUE | (irr ? EDGE_IRREDUCIBLE_LOOP : 0)); + then_old_edge = make_edge (then_bb, old_dest, + EDGE_FALLTHRU | (irr ? EDGE_IRREDUCIBLE_LOOP : 0)); set_immediate_dominator (CDI_DOMINATORS, then_bb, new_bb); diff --git a/gcc-4.9/gcc/tree-ssa-propagate.c b/gcc-4.9/gcc/tree-ssa-propagate.c index 840d7e762..172b6386e 100644 --- a/gcc-4.9/gcc/tree-ssa-propagate.c +++ b/gcc-4.9/gcc/tree-ssa-propagate.c @@ -571,8 +571,18 @@ valid_gimple_rhs_p (tree expr) /* All constants are ok. */ break; - case tcc_binary: case tcc_comparison: + /* GENERIC allows comparisons with non-boolean types, reject + those for GIMPLE. Let vector-typed comparisons pass - rules + for GENERIC and GIMPLE are the same here. */ + if (!(INTEGRAL_TYPE_P (TREE_TYPE (expr)) + && (TREE_CODE (TREE_TYPE (expr)) == BOOLEAN_TYPE + || TYPE_PRECISION (TREE_TYPE (expr)) == 1)) + && TREE_CODE (TREE_TYPE (expr)) != VECTOR_TYPE) + return false; + + /* Fallthru. */ + case tcc_binary: if (!is_gimple_val (TREE_OPERAND (expr, 0)) || !is_gimple_val (TREE_OPERAND (expr, 1))) return false; diff --git a/gcc-4.9/gcc/tree-ssa-reassoc.c b/gcc-4.9/gcc/tree-ssa-reassoc.c index e9e29e550..fce2a6e20 100644 --- a/gcc-4.9/gcc/tree-ssa-reassoc.c +++ b/gcc-4.9/gcc/tree-ssa-reassoc.c @@ -221,6 +221,35 @@ static struct pointer_map_t *operand_rank; static long get_rank (tree); static bool reassoc_stmt_dominates_stmt_p (gimple, gimple); +/* Wrapper around gsi_remove, which adjusts gimple_uid of debug stmts + possibly added by gsi_remove. */ + +bool +reassoc_remove_stmt (gimple_stmt_iterator *gsi) +{ + gimple stmt = gsi_stmt (*gsi); + + if (!MAY_HAVE_DEBUG_STMTS || gimple_code (stmt) == GIMPLE_PHI) + return gsi_remove (gsi, true); + + gimple_stmt_iterator prev = *gsi; + gsi_prev (&prev); + unsigned uid = gimple_uid (stmt); + basic_block bb = gimple_bb (stmt); + bool ret = gsi_remove (gsi, true); + if (!gsi_end_p (prev)) + gsi_next (&prev); + else + prev = gsi_start_bb (bb); + gimple end_stmt = gsi_stmt (*gsi); + while ((stmt = gsi_stmt (prev)) != end_stmt) + { + gcc_assert (stmt && is_gimple_debug (stmt) && gimple_uid (stmt) == 0); + gimple_set_uid (stmt, uid); + gsi_next (&prev); + } + return ret; +} /* Bias amount for loop-carried phis. We want this to be larger than the depth of any reassociation tree we can see, but not larger than @@ -1123,7 +1152,7 @@ propagate_op_to_single_use (tree op, gimple stmt, tree *def) update_stmt (use_stmt); gsi = gsi_for_stmt (stmt); unlink_stmt_vdef (stmt); - gsi_remove (&gsi, true); + reassoc_remove_stmt (&gsi); release_defs (stmt); } @@ -3072,7 +3101,7 @@ remove_visited_stmt_chain (tree var) { var = gimple_assign_rhs1 (stmt); gsi = gsi_for_stmt (stmt); - gsi_remove (&gsi, true); + reassoc_remove_stmt (&gsi); release_defs (stmt); } else @@ -3494,7 +3523,7 @@ linearize_expr (gimple stmt) update_stmt (stmt); gsi = gsi_for_stmt (oldbinrhs); - gsi_remove (&gsi, true); + reassoc_remove_stmt (&gsi); release_defs (oldbinrhs); gimple_set_visited (stmt, true); @@ -3896,7 +3925,7 @@ repropagate_negates (void) gimple_assign_set_rhs_with_ops (&gsi2, NEGATE_EXPR, x, NULL); user = gsi_stmt (gsi2); update_stmt (user); - gsi_remove (&gsi, true); + reassoc_remove_stmt (&gsi); release_defs (feed); plus_negates.safe_push (gimple_assign_lhs (user)); } @@ -4413,7 +4442,7 @@ reassociate_bb (basic_block bb) reassociations. */ if (has_zero_uses (gimple_get_lhs (stmt))) { - gsi_remove (&gsi, true); + reassoc_remove_stmt (&gsi); release_defs (stmt); /* We might end up removing the last stmt above which places the iterator to the end of the sequence. diff --git a/gcc-4.9/gcc/tree-ssa-structalias.c b/gcc-4.9/gcc/tree-ssa-structalias.c index 8201cb423..347dba3e9 100644 --- a/gcc-4.9/gcc/tree-ssa-structalias.c +++ b/gcc-4.9/gcc/tree-ssa-structalias.c @@ -7264,10 +7264,7 @@ ipa_pta_execute (void) tree ptr; struct function *fn; unsigned i; - varinfo_t fi; basic_block bb; - struct pt_solution uses, clobbers; - struct cgraph_edge *e; /* Nodes without a body are not interesting. */ if (!cgraph_function_with_gimple_body_p (node) || node->clone_of) @@ -7283,21 +7280,6 @@ ipa_pta_execute (void) find_what_p_points_to (ptr); } - /* Compute the call-use and call-clobber sets for all direct calls. */ - fi = lookup_vi_for_tree (node->decl); - gcc_assert (fi->is_fn_info); - clobbers - = find_what_var_points_to (first_vi_for_offset (fi, fi_clobbers)); - uses = find_what_var_points_to (first_vi_for_offset (fi, fi_uses)); - for (e = node->callers; e; e = e->next_caller) - { - if (!e->call_stmt) - continue; - - *gimple_call_clobber_set (e->call_stmt) = clobbers; - *gimple_call_use_set (e->call_stmt) = uses; - } - /* Compute the call-use and call-clobber sets for indirect calls and calls to external functions. */ FOR_EACH_BB_FN (bb, fn) @@ -7308,17 +7290,27 @@ ipa_pta_execute (void) { gimple stmt = gsi_stmt (gsi); struct pt_solution *pt; - varinfo_t vi; + varinfo_t vi, fi; tree decl; if (!is_gimple_call (stmt)) continue; - /* Handle direct calls to external functions. */ + /* Handle direct calls to functions with body. */ decl = gimple_call_fndecl (stmt); if (decl - && (!(fi = lookup_vi_for_tree (decl)) - || !fi->is_fn_info)) + && (fi = lookup_vi_for_tree (decl)) + && fi->is_fn_info) + { + *gimple_call_clobber_set (stmt) + = find_what_var_points_to + (first_vi_for_offset (fi, fi_clobbers)); + *gimple_call_use_set (stmt) + = find_what_var_points_to + (first_vi_for_offset (fi, fi_uses)); + } + /* Handle direct calls to external functions. */ + else if (decl) { pt = gimple_call_use_set (stmt); if (gimple_call_flags (stmt) & ECF_CONST) @@ -7362,10 +7354,9 @@ ipa_pta_execute (void) pt->nonlocal = 1; } } - /* Handle indirect calls. */ - if (!decl - && (fi = get_fi_for_callee (stmt))) + else if (!decl + && (fi = get_fi_for_callee (stmt))) { /* We need to accumulate all clobbers/uses of all possible callees. */ diff --git a/gcc-4.9/gcc/tree-ssa-threadedge.c b/gcc-4.9/gcc/tree-ssa-threadedge.c index c447b72c3..8e628d553 100644 --- a/gcc-4.9/gcc/tree-ssa-threadedge.c +++ b/gcc-4.9/gcc/tree-ssa-threadedge.c @@ -387,7 +387,34 @@ record_temporary_equivalences_from_stmts_at_dest (edge e, && (gimple_code (stmt) != GIMPLE_CALL || gimple_call_lhs (stmt) == NULL_TREE || TREE_CODE (gimple_call_lhs (stmt)) != SSA_NAME)) - continue; + { + /* STMT might still have DEFS and we need to invalidate any known + equivalences for them. + + Consider if STMT is a GIMPLE_ASM with one or more outputs that + feeds a conditional inside a loop. We might derive an equivalence + due to the conditional. */ + tree op; + ssa_op_iter iter; + + if (backedge_seen) + FOR_EACH_SSA_TREE_OPERAND (op, stmt, iter, SSA_OP_DEF) + { + /* This call only invalidates equivalences created by + PHI nodes. This is by design to keep the cost of + of invalidation reasonable. */ + invalidate_equivalences (op, stack, src_map, dst_map); + + /* However, conditionals can imply values for real + operands as well. And those won't be recorded in the + maps. In fact, those equivalences may be recorded totally + outside the threading code. We can just create a new + temporary NULL equivalence here. */ + record_temporary_equivalence (op, NULL_TREE, stack); + } + + continue; + } /* The result of __builtin_object_size depends on all the arguments of a phi node. Temporarily using only one edge produces invalid @@ -939,9 +966,14 @@ thread_around_empty_blocks (edge taken_edge, SIMPLIFY is a pass-specific function used to simplify statements. Our caller is responsible for restoring the state of the expression - and const_and_copies stacks. */ + and const_and_copies stacks. -static bool + Positive return value is success. Zero return value is failure, but + the block can still be duplicated as a joiner in a jump thread path, + negative indicates the block should not be duplicated and thus is not + suitable for a joiner in a jump threading path. */ + +static int thread_through_normal_block (edge e, gimple dummy_cond, bool handle_dominating_asserts, @@ -963,7 +995,7 @@ thread_through_normal_block (edge e, /* PHIs create temporary equivalences. */ if (!record_temporary_equivalences_from_phis (e, stack, *backedge_seen_p, src_map, dst_map)) - return false; + return 0; /* Now walk each statement recording any context sensitive temporary equivalences we can detect. */ @@ -971,8 +1003,16 @@ thread_through_normal_block (edge e, = record_temporary_equivalences_from_stmts_at_dest (e, stack, simplify, *backedge_seen_p, src_map, dst_map); + + /* If we didn't look at all the statements, the most likely reason is + there were too many and thus duplicating this block is not profitable. + + Also note if we do not look at all the statements, then we may not + have invalidated equivalences that are no longer valid if we threaded + around a loop. Thus we must signal to our caller that this block + is not suitable for use as a joiner in a threading path. */ if (!stmt) - return false; + return -1; /* If we stopped at a COND_EXPR or SWITCH_EXPR, see if we know which arm will be taken. */ @@ -996,7 +1036,7 @@ thread_through_normal_block (edge e, if (dest == NULL || dest == e->dest || bitmap_bit_p (visited, dest->index)) - return false; + return 0; /* Only push the EDGE_START_JUMP_THREAD marker if this is first edge on the path. */ @@ -1030,10 +1070,10 @@ thread_through_normal_block (edge e, visited, path, backedge_seen_p); - return true; + return 1; } } - return false; + return 0; } /* We are exiting E->src, see if E->dest ends with a conditional @@ -1085,9 +1125,12 @@ thread_across_edge (gimple dummy_cond, if (backedge_seen) simplify = dummy_simplify; - if (thread_through_normal_block (e, dummy_cond, handle_dominating_asserts, - stack, simplify, path, visited, - &backedge_seen, src_map, dst_map)) + int threaded = thread_through_normal_block (e, dummy_cond, + handle_dominating_asserts, + stack, simplify, path, + visited, &backedge_seen, + src_map, dst_map); + if (threaded > 0) { propagate_threaded_block_debug_into (path->last ()->e->dest, e->dest); @@ -1100,10 +1143,27 @@ thread_across_edge (gimple dummy_cond, } else { - /* There should be no edges on the path, so no need to walk through - the vector entries. */ + /* Negative and zero return values indicate no threading was possible, + thus there should be no edges on the thread path and no need to walk + through the vector entries. */ gcc_assert (path->length () == 0); path->release (); + + /* A negative status indicates the target block was deemed too big to + duplicate. Just quit now rather than trying to use the block as + a joiner in a jump threading path. + + This prevents unnecessary code growth, but more importantly if we + do not look at all the statements in the block, then we may have + missed some invalidations if we had traversed a backedge! */ + if (threaded < 0) + { + BITMAP_FREE (visited); + BITMAP_FREE (src_map); + BITMAP_FREE (dst_map); + remove_temporary_equivalences (stack); + return; + } } /* We were unable to determine what out edge from E->dest is taken. However, @@ -1185,7 +1245,7 @@ thread_across_edge (gimple dummy_cond, handle_dominating_asserts, stack, simplify, path, visited, &backedge_seen, - src_map, dst_map); + src_map, dst_map) > 0; /* If we were able to thread through a successor of E->dest, then record the jump threading opportunity. */ diff --git a/gcc-4.9/gcc/tree-tailcall.c b/gcc-4.9/gcc/tree-tailcall.c index 3488c2fc2..02086317b 100644 --- a/gcc-4.9/gcc/tree-tailcall.c +++ b/gcc-4.9/gcc/tree-tailcall.c @@ -285,9 +285,19 @@ process_assignment (gimple stmt, gimple_stmt_iterator call, tree *m, { /* Reject a tailcall if the type conversion might need additional code. */ - if (gimple_assign_cast_p (stmt) - && TYPE_MODE (TREE_TYPE (dest)) != TYPE_MODE (TREE_TYPE (src_var))) - return false; + if (gimple_assign_cast_p (stmt)) + { + if (TYPE_MODE (TREE_TYPE (dest)) != TYPE_MODE (TREE_TYPE (src_var))) + return false; + + /* Even if the type modes are the same, if the precision of the + type is smaller than mode's precision, + reduce_to_bit_field_precision would generate additional code. */ + if (INTEGRAL_TYPE_P (TREE_TYPE (dest)) + && (GET_MODE_PRECISION (TYPE_MODE (TREE_TYPE (dest))) + > TYPE_PRECISION (TREE_TYPE (dest)))) + return false; + } if (src_var != *ass_var) return false; diff --git a/gcc-4.9/gcc/tree-vect-data-refs.c b/gcc-4.9/gcc/tree-vect-data-refs.c index fbc35a3fe..274cdbdcf 100644 --- a/gcc-4.9/gcc/tree-vect-data-refs.c +++ b/gcc-4.9/gcc/tree-vect-data-refs.c @@ -3172,7 +3172,7 @@ vect_check_gather (gimple stmt, loop_vec_info loop_vinfo, tree *basep, bool vect_analyze_data_refs (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, - int *min_vf) + int *min_vf, unsigned *n_stmts) { struct loop *loop = NULL; basic_block bb = NULL; @@ -3207,6 +3207,9 @@ vect_analyze_data_refs (loop_vec_info loop_vinfo, for (gsi = gsi_start_bb (bbs[i]); !gsi_end_p (gsi); gsi_next (&gsi)) { gimple stmt = gsi_stmt (gsi); + if (is_gimple_debug (stmt)) + continue; + ++*n_stmts; if (!find_data_references_in_stmt (loop, stmt, &datarefs)) { if (is_gimple_call (stmt) && loop->safelen) @@ -3260,6 +3263,9 @@ vect_analyze_data_refs (loop_vec_info loop_vinfo, for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) { gimple stmt = gsi_stmt (gsi); + if (is_gimple_debug (stmt)) + continue; + ++*n_stmts; if (!find_data_references_in_stmt (NULL, stmt, &BB_VINFO_DATAREFS (bb_vinfo))) { diff --git a/gcc-4.9/gcc/tree-vect-generic.c b/gcc-4.9/gcc/tree-vect-generic.c index d00a4b47e..a1de7beb0 100644 --- a/gcc-4.9/gcc/tree-vect-generic.c +++ b/gcc-4.9/gcc/tree-vect-generic.c @@ -971,7 +971,8 @@ expand_vector_operation (gimple_stmt_iterator *gsi, tree type, tree compute_type if (!optimize || !VECTOR_INTEGER_TYPE_P (type) - || TREE_CODE (rhs2) != VECTOR_CST) + || TREE_CODE (rhs2) != VECTOR_CST + || !VECTOR_MODE_P (TYPE_MODE (type))) break; ret = expand_vector_divmod (gsi, type, rhs1, rhs2, code); diff --git a/gcc-4.9/gcc/tree-vect-loop.c b/gcc-4.9/gcc/tree-vect-loop.c index 1c78e114f..4204907a1 100644 --- a/gcc-4.9/gcc/tree-vect-loop.c +++ b/gcc-4.9/gcc/tree-vect-loop.c @@ -1629,6 +1629,7 @@ vect_analyze_loop_2 (loop_vec_info loop_vinfo) int max_vf = MAX_VECTORIZATION_FACTOR; int min_vf = 2; unsigned int th; + unsigned int n_stmts = 0; /* Find all data references in the loop (which correspond to vdefs/vuses) and analyze their evolution in the loop. Also adjust the minimal @@ -1637,7 +1638,7 @@ vect_analyze_loop_2 (loop_vec_info loop_vinfo) FORNOW: Handle only simple, array references, which alignment can be forced, and aligned pointer-references. */ - ok = vect_analyze_data_refs (loop_vinfo, NULL, &min_vf); + ok = vect_analyze_data_refs (loop_vinfo, NULL, &min_vf, &n_stmts); if (!ok) { if (dump_enabled_p ()) @@ -1747,7 +1748,7 @@ vect_analyze_loop_2 (loop_vec_info loop_vinfo) } /* Check the SLP opportunities in the loop, analyze and build SLP trees. */ - ok = vect_analyze_slp (loop_vinfo, NULL); + ok = vect_analyze_slp (loop_vinfo, NULL, n_stmts); if (ok) { /* Decide which possible SLP instances to SLP. */ @@ -3951,8 +3952,12 @@ vect_create_epilog_for_reduction (vec vect_defs, gimple stmt, /* Set phi nodes arguments. */ FOR_EACH_VEC_ELT (reduction_phis, i, phi) { - tree vec_init_def = vec_initial_defs[i]; - tree def = vect_defs[i]; + tree vec_init_def, def; + gimple_seq stmts; + vec_init_def = force_gimple_operand (vec_initial_defs[i], &stmts, + true, NULL_TREE); + gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts); + def = vect_defs[i]; for (j = 0; j < ncopies; j++) { /* Set the loop-entry arg of the reduction-phi. */ diff --git a/gcc-4.9/gcc/tree-vect-slp.c b/gcc-4.9/gcc/tree-vect-slp.c index 65f8b022e..0ab267f7d 100644 --- a/gcc-4.9/gcc/tree-vect-slp.c +++ b/gcc-4.9/gcc/tree-vect-slp.c @@ -849,9 +849,10 @@ vect_build_slp_tree (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, unsigned int *max_nunits, vec *loads, unsigned int vectorization_factor, - bool *matches, unsigned *npermutes) + bool *matches, unsigned *npermutes, unsigned *tree_size, + unsigned max_tree_size) { - unsigned nops, i, this_npermutes = 0; + unsigned nops, i, this_npermutes = 0, this_tree_size = 0; gimple stmt; if (!matches) @@ -911,6 +912,12 @@ vect_build_slp_tree (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, if (oprnd_info->first_dt != vect_internal_def) continue; + if (++this_tree_size > max_tree_size) + { + vect_free_oprnd_info (oprnds_info); + return false; + } + child = vect_create_new_slp_node (oprnd_info->def_stmts); if (!child) { @@ -921,7 +928,8 @@ vect_build_slp_tree (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, bool *matches = XALLOCAVEC (bool, group_size); if (vect_build_slp_tree (loop_vinfo, bb_vinfo, &child, group_size, max_nunits, loads, - vectorization_factor, matches, npermutes)) + vectorization_factor, matches, + npermutes, &this_tree_size, max_tree_size)) { oprnd_info->def_stmts = vNULL; SLP_TREE_CHILDREN (*node).quick_push (child); @@ -961,7 +969,8 @@ vect_build_slp_tree (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, if (vect_build_slp_tree (loop_vinfo, bb_vinfo, &child, group_size, max_nunits, loads, vectorization_factor, - matches, npermutes)) + matches, npermutes, &this_tree_size, + max_tree_size)) { oprnd_info->def_stmts = vNULL; SLP_TREE_CHILDREN (*node).quick_push (child); @@ -977,6 +986,9 @@ vect_build_slp_tree (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, return false; } + if (tree_size) + *tree_size += this_tree_size; + vect_free_oprnd_info (oprnds_info); return true; } @@ -1436,7 +1448,7 @@ vect_analyze_slp_cost (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, static bool vect_analyze_slp_instance (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, - gimple stmt) + gimple stmt, unsigned max_tree_size) { slp_instance new_instance; slp_tree node; @@ -1536,7 +1548,8 @@ vect_analyze_slp_instance (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, /* Build the tree for the SLP instance. */ if (vect_build_slp_tree (loop_vinfo, bb_vinfo, &node, group_size, &max_nunits, &loads, - vectorization_factor, NULL, NULL)) + vectorization_factor, NULL, NULL, NULL, + max_tree_size)) { /* Calculate the unrolling factor based on the smallest type. */ if (max_nunits > nunits) @@ -1641,7 +1654,8 @@ vect_analyze_slp_instance (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, trees of packed scalar stmts if SLP is possible. */ bool -vect_analyze_slp (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo) +vect_analyze_slp (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo, + unsigned max_tree_size) { unsigned int i; vec grouped_stores; @@ -1664,7 +1678,8 @@ vect_analyze_slp (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo) /* Find SLP sequences starting from groups of grouped stores. */ FOR_EACH_VEC_ELT (grouped_stores, i, first_element) - if (vect_analyze_slp_instance (loop_vinfo, bb_vinfo, first_element)) + if (vect_analyze_slp_instance (loop_vinfo, bb_vinfo, first_element, + max_tree_size)) ok = true; if (bb_vinfo && !ok) @@ -1681,7 +1696,8 @@ vect_analyze_slp (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo) { /* Find SLP sequences starting from reduction chains. */ FOR_EACH_VEC_ELT (reduc_chains, i, first_element) - if (vect_analyze_slp_instance (loop_vinfo, bb_vinfo, first_element)) + if (vect_analyze_slp_instance (loop_vinfo, bb_vinfo, first_element, + max_tree_size)) ok = true; else return false; @@ -1693,7 +1709,8 @@ vect_analyze_slp (loop_vec_info loop_vinfo, bb_vec_info bb_vinfo) /* Find SLP sequences starting from groups of reductions. */ if (loop_vinfo && LOOP_VINFO_REDUCTIONS (loop_vinfo).length () > 1 - && vect_analyze_slp_instance (loop_vinfo, bb_vinfo, reductions[0])) + && vect_analyze_slp_instance (loop_vinfo, bb_vinfo, reductions[0], + max_tree_size)) ok = true; return true; @@ -2071,12 +2088,13 @@ vect_slp_analyze_bb_1 (basic_block bb) slp_instance instance; int i; int min_vf = 2; + unsigned n_stmts = 0; bb_vinfo = new_bb_vec_info (bb); if (!bb_vinfo) return NULL; - if (!vect_analyze_data_refs (NULL, bb_vinfo, &min_vf)) + if (!vect_analyze_data_refs (NULL, bb_vinfo, &min_vf, &n_stmts)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -2124,7 +2142,7 @@ vect_slp_analyze_bb_1 (basic_block bb) /* Check the SLP opportunities in the basic block, analyze and build SLP trees. */ - if (!vect_analyze_slp (NULL, bb_vinfo)) + if (!vect_analyze_slp (NULL, bb_vinfo, n_stmts)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, diff --git a/gcc-4.9/gcc/tree-vectorizer.h b/gcc-4.9/gcc/tree-vectorizer.h index f2087e223..fa2989d72 100644 --- a/gcc-4.9/gcc/tree-vectorizer.h +++ b/gcc-4.9/gcc/tree-vectorizer.h @@ -1057,7 +1057,8 @@ extern bool vect_analyze_data_ref_accesses (loop_vec_info, bb_vec_info); extern bool vect_prune_runtime_alias_test_list (loop_vec_info); extern tree vect_check_gather (gimple, loop_vec_info, tree *, tree *, int *); -extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *); +extern bool vect_analyze_data_refs (loop_vec_info, bb_vec_info, int *, + unsigned *); extern tree vect_create_data_ref_ptr (gimple, tree, struct loop *, tree, tree *, gimple_stmt_iterator *, gimple *, bool, bool *); @@ -1107,7 +1108,7 @@ extern bool vect_transform_slp_perm_load (slp_tree, vec , slp_instance, bool); extern bool vect_schedule_slp (loop_vec_info, bb_vec_info); extern void vect_update_slp_costs_according_to_vf (loop_vec_info); -extern bool vect_analyze_slp (loop_vec_info, bb_vec_info); +extern bool vect_analyze_slp (loop_vec_info, bb_vec_info, unsigned); extern bool vect_make_slp_decision (loop_vec_info); extern void vect_detect_hybrid_slp (loop_vec_info); extern void vect_get_slp_defs (vec , slp_tree, diff --git a/gcc-4.9/gcc/tree.h b/gcc-4.9/gcc/tree.h index 9fbc5c4ec..90e5e275c 100644 --- a/gcc-4.9/gcc/tree.h +++ b/gcc-4.9/gcc/tree.h @@ -1330,6 +1330,9 @@ extern void protected_set_expr_location (tree, location_t); #define OMP_CLAUSE_LINEAR_STEP(NODE) \ OMP_CLAUSE_OPERAND (OMP_CLAUSE_SUBCODE_CHECK (NODE, OMP_CLAUSE_LINEAR), 1) +#define OMP_CLAUSE_LINEAR_GIMPLE_SEQ(NODE) \ + (OMP_CLAUSE_CHECK (NODE))->omp_clause.gimple_reduction_init + #define OMP_CLAUSE_ALIGNED_ALIGNMENT(NODE) \ OMP_CLAUSE_OPERAND (OMP_CLAUSE_SUBCODE_CHECK (NODE, OMP_CLAUSE_ALIGNED), 1) -- cgit v1.2.3